公开(公告)号：US20070010032A1

公开(公告)日：2007-01-11

申请号：US11519614

申请日：2006-09-12

申请人： Oliver Patterson ,  David Shuttleworth ,  Bradley Albers ,  Werner Weck ,  Gregory Brown

发明人： Oliver Patterson ,  David Shuttleworth ,  Bradley Albers ,  Werner Weck ,  Gregory Brown

IPC分类号： H01L21/00

CPC分类号： H01L22/20 ,  G01R31/2894 ,  H01L21/76892

摘要： A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.

摘要翻译： 通过在制造过程中对缺陷的在线修复来提高半导体产量的方法包括：在模具上形成所选择的层之后检查晶片上的管芯，识别每个管芯中的缺陷，将所识别的缺陷分类为杀伤或非关键的， 对于每个杀手缺陷，确定纠正缺陷的动作，修复缺陷并将晶片返回到下一个处理步骤。 还公开了一种通过将模具分成网格并利用网格分析来找到最小侵入性修复来确定有效修复过程的方法。

公开(公告)号：US20050255611A1

公开(公告)日：2005-11-17

申请号：US10911142

申请日：2004-08-04

申请人： Oliver Patterson ,  David Shuttleworth ,  Bradley Albers ,  Werner Weck ,  Gregory Brown

发明人： Oliver Patterson ,  David Shuttleworth ,  Bradley Albers ,  Werner Weck ,  Gregory Brown

IPC分类号： G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L21/768

CPC分类号： H01L22/20 ,  G01R31/2894 ,  H01L21/76892

摘要： A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.

摘要翻译： 通过在制造过程中对缺陷的在线修复来提高半导体产量的方法包括：在模具上形成所选择的层之后检查晶片上的管芯，识别每个管芯中的缺陷，将所识别的缺陷分类为杀伤或非关键的， 对于每个杀手缺陷，确定纠正缺陷的动作，修复缺陷并将晶片返回到下一个处理步骤。 还公开了一种通过将模具分成网格并利用网格分析来找到最小侵入性修复来确定有效修复过程的方法。

公开(公告)号：US20060063282A1

公开(公告)日：2006-03-23

申请号：US10947069

申请日：2004-09-22

申请人： Bradley Albers ,  Thomas Esry ,  Daniel Kerr ,  Edward Martin ,  Oliver Patterson

发明人： Bradley Albers ,  Thomas Esry ,  Daniel Kerr ,  Edward Martin ,  Oliver Patterson

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  G01R31/2648 ,  G01R31/2884 ,  G01R31/307

摘要： A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.

摘要翻译： 用于识别NPN双极晶体管的发射极 - 基极结中的晶体缺陷的方法和装置使用具有可以使用无源电压对比度检查的NP结的测试结构。 测试结构消除了晶体管的集电极，仅模拟发射极和基极。 如果发射极 - 基极结有缺陷，则消除集电极会消除晶片的集电极和衬底之间的NP结，从而允许电荷从衬底流到发射极，因为在测试结构中只有一个NP结存在。 在一个实施例中，测试结构位于晶片上的管芯之间，并且可以形成为几千个。

公开(公告)号：US20060087401A1

公开(公告)日：2006-04-27

申请号：US10953478

申请日：2004-09-29

申请人： Daniel Kerr ,  Roger Key ,  Bradley Albers ,  William Russell ,  Alan Chen

发明人： Daniel Kerr ,  Roger Key ,  Bradley Albers ,  William Russell ,  Alan Chen

IPC分类号： H01C1/012

CPC分类号： H01L23/5228 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resistor formed on a material layer of a semiconductor integrated circuit and a method for forming the resistor. The resistor comprises a region of resistive material with a plurality of conductive contacts or plugs in electrical contact with and extending away from the resistive material. A first and a second interconnect line are formed overlying the plugs and in conductive contact with one or more of the plurality of plugs, such that a portion of the resistive material between the first and the second interconnect lines provides a desired resistance. According to a method of the present invention, the plurality of conductive contacts are formed using a first photolithographic mask and the first and the second interconnect lines are formed using a second photolithographic mask. The desired resistance is changed by modifying the first or the second mask such that one or more dimensions of a region of the resistive material between the first and the second interconnect lines is altered.

摘要翻译： 形成在半导体集成电路的材料层上的电阻器和形成该电阻器的方法。 电阻器包括电阻材料的区域，其具有与电阻材料电接触并远离电阻材料的多个导电触点或插塞。 第一和第二互连线形成在插头上方并与多个插头中的一个或多个导电接触，使得第一和第二互连线之间的电阻材料的一部分提供期望的电阻。 根据本发明的方法，使用第一光刻掩模形成多个导电触点，并且使用第二光刻掩模形成第一和第二布线。 通过修改第一或第二掩模来改变期望的电阻，使得在第一和第二互连线之间的电阻材料的区域的一个或多个维度被改变。