公开(公告)号：US06756279B2

公开(公告)日：2004-06-29

申请号：US10209190

申请日：2002-07-30

申请人： Olivier Menut ,  Hervé Jaouen ,  Guillaume Bouche

发明人： Olivier Menut ,  Hervé Jaouen ,  Guillaume Bouche

IPC分类号： H01L218228

CPC分类号： H01L29/66272 ,  H01L21/8249

摘要： A method for manufacturing a contact between a semiconductor substrate and a doped polysilicon layer deposited on the substrate with an interposed insulating layer, wherein elements adapted to making the insulating layer permeable to the migration of dopants from the polysilicon layer to the substrate are implanted.

摘要翻译： 一种用于制造半导体衬底和沉积在具有中间绝缘层的衬底上的掺杂多晶硅层之间的接触的方法，其中植入适于使掺杂剂从多晶硅层迁移至衬底的绝缘层可渗透的元件。

公开(公告)号：US06503812B2

公开(公告)日：2003-01-07

申请号：US10044829

申请日：2002-01-11

申请人： Olivier Menut ,  Guillaume Bouche ,  Herve Jaouen

发明人： Olivier Menut ,  Guillaume Bouche ,  Herve Jaouen

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283

摘要： The semiconductor device comprises a semiconductor substrate (SB) having locally at least one zone (ZL) terminating in the surface of the substrate and entirely bordered, along its lateral edges and its bottom, by an insulating material so as to be completely isolated from the rest of the substrate. The horizontal isolating layer may be a layer of constant thickness or a crenellated layer.

摘要翻译： 半导体器件包括半导体衬底（SB），其具有局部至少一个区域（ZL），该区域（ZL）终止于衬底的表面，并且沿着其侧边缘及其底部通过绝缘材料整齐地界定，从而与绝缘材料完全隔离 底物的剩余部分。 水平隔离层可以是恒定厚度的层或钝化层。

公开(公告)号：US07488653B2

公开(公告)日：2009-02-10

申请号：US11687413

申请日：2007-03-16

申请人： Olivier Menut ,  Nicolas Planes ,  Sylvie Del Medico

发明人： Olivier Menut ,  Nicolas Planes ,  Sylvie Del Medico

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device includes a substrate of a first type of conductivity provided with at least one gate on one of its faces, and at least two doped regions of a second type of conductivity for forming a drain region and a source region. The two doped regions are arranged in the substrate flush with the face of the substrate on each side of a region of the substrate located under the gate for forming a channel between the drain and source regions. At least one region of doping agents of the second type of conductivity is implanted only in the channel.

摘要翻译： 半导体器件包括第一类导电性的衬底，该衬底在其一个面上具有至少一个栅极，以及至少两个第二导电类型的掺杂区域，用于形成漏极区域和源极区域。 两个掺杂区域布置在衬底中的衬底的面上与位于栅极下方的衬底的区域的每一侧齐平，以形成漏极和源极区域之间的沟道。 至少一个第二类导电性掺杂剂的区域仅植入通道中。

公开(公告)号：US07115933B2

公开(公告)日：2006-10-03

申请号：US10466145

申请日：2002-01-09

申请人： Olivier Menut ,  Yvon Gris

发明人： Olivier Menut ,  Yvon Gris

IPC分类号： H01L27/108 ,  H01L27/10 ,  H01L29/68

CPC分类号： H01L29/808 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/14683

摘要： An integrated circuit has at least one semiconductor device for storing charge that includes at least one elementary active component and at least one elementary storage capacitor. The device includes a substrate having a lower region containing at least one buried capacitive elementary trench forming the elementary storage capacitor, and an elementary well located above the lower region of the substrate and isolated laterally by a lateral electrical isolation region. The elementary active component is located in the elementary well or in and on the elementary well. The capacitive elementary trench is located under the elementary active component and is in electrical contact with the elementary well. In one preferred embodiment, the lateral electrical isolation region is formed by a trench filled with a dielectric material and has a greater depth than that of the elementary well. Also provided is a method for fabricating an integrated circuit that includes a semiconductor device for storing charge.

摘要翻译： 集成电路具有至少一个用于存储包含至少一个基本有源分量和至少一个基本存储电容器的电荷的半导体器件。 该器件包括具有形成基本存储电容器的至少一个掩埋电容元件沟槽的下部区域的基板，以及位于该基板的下部区域上方并由横向电隔离区域侧向隔离的基本阱。 基本活性成分位于基本井中，或位于基本井中。 电容性基本沟槽位于基本有源分量之下并与基本阱电接触。 在一个优选实施例中，横向电绝缘区由填充有电介质材料的沟槽形成，并且具有比基本阱更深的深度。 还提供了一种用于制造集成电路的方法，该集成电路包括用于存储电荷的半导体器件。

公开(公告)号：US06897545B2

公开(公告)日：2005-05-24

申请号：US10142249

申请日：2002-05-09

申请人： Olivier Menut ,  Herve Jaouen

发明人： Olivier Menut ,  Herve Jaouen

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L27/102

CPC分类号： H01L29/1012 ,  H01L29/0649 ,  H01L29/735

摘要： The transistor includes an emitter region 17 disposed in a first isolating well 11, 150 formed in a semiconductor bulk. An extrinsic collector region 16 is disposed in a second isolating well 3, 150 formed in the semiconductor bulk SB and separated laterally from the first well by a bulk separator area 20. An intrinsic collector region is situated in the bulk separator area 20 in contact with the extrinsic collector region. An intrinsic base region 100 is formed which is thinner laterally than vertically and in contact with the intrinsic collector region and in contact with the emitter region through bearing on a vertical flank of the first isolating well facing a vertical flank of the second isolating well. An extrinsic base region 60 is formed which is substantially perpendicular to the intrinsic base region in the top part of the bulk separator area, and contact terminals C, B, E respectively in contact with the extrinsic collector region, the extrinsic base region, and the emitter region.

摘要翻译： 晶体管包括设置在半导体本体中形成的第一隔离阱11,150中的发射极区17。 外部集电极区域16设置在形成于半导体本体SB中的第二隔离阱3,150中，并且通过体分离器区域20与第一阱横向分离。 内部集电极区域位于与外部集电极区域接触的体分离器区域20中。 形成本征基区100，其横向比垂直地更薄并且与本征收集区相接触，并且通过轴承在第一隔离井的垂直侧面与第二隔离井的垂直侧面的垂直侧面接触。 形成基本上垂直于本体分离器区域的顶部中的本征基极区域的外部基极区域60，以及分别与外部基极区域，外部基极区域和外部基极区域接触的接触端子C，B，E 发射区。

公开(公告)号：US08736061B2

公开(公告)日：2014-05-27

申请号：US13490840

申请日：2012-06-07

申请人： Frank Johnson ,  Olivier Menut ,  Marc Tarabbia ,  Gregory A. Northrop

发明人： Frank Johnson ,  Olivier Menut ,  Marc Tarabbia ,  Gregory A. Northrop

IPC分类号： H01L23/52

CPC分类号： H01L27/0207 ,  H01L23/5286 ,  H01L27/11807 ,  H01L2027/11859 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括具有第一边界，与第一边界相反的第二边界，互连第一和第二边界的第三边界以及与第三边界相对的第四边界并互连第一和第二边界的标准单元。 标准单元还包括从第一边界延伸到第二边界的并行有效区域。 此外，标准单元具有从第三边界延伸到第四边界并且在有源区上延伸的平行栅极条。 切割掩模覆盖门条。 互连件定位在切割掩模上方并与选定的栅条形成电连接。

公开(公告)号：US20070015326A1

公开(公告)日：2007-01-18

申请号：US11533939

申请日：2006-09-21

申请人： Olivier Menut ,  Yvon Gris

发明人： Olivier Menut ,  Yvon Gris

IPC分类号： H01L21/8238

CPC分类号： H01L29/808 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/14683

摘要： An integrated circuit has at least one semiconductor device for storing charge that includes at least one elementary active component and at least one elementary storage capacitor. The device includes a substrate having a lower region containing at least one buried capacitive elementary trench forming the elementary storage capacitor, and an elementary well located above the lower region of the substrate and isolated laterally by a lateral electrical isolation region. The elementary active component is located in the elementary well or in and on the elementary well. The capacitive elementary trench is located under the elementary active component and is in electrical contact with the elementary well. In one preferred embodiment, the lateral electrical isolation region is formed by a trench filled with a dielectric material and has a greater depth than that of the elementary well. Also provided is a method for fabricating an integrated circuit that includes a semiconductor device for storing charge.

摘要翻译： 集成电路具有至少一个用于存储包含至少一个基本有源分量和至少一个基本存储电容器的电荷的半导体器件。 该器件包括具有形成基本存储电容器的至少一个掩埋电容元件沟槽的下部区域的基板，以及位于该基板的下部区域上方并由横向电隔离区域侧向隔离的基本阱。 基本活性成分位于基本井中，或位于基本井中。 电容性基本沟槽位于基本有源分量之下并与基本阱电接触。 在一个优选实施例中，横向电绝缘区由填充有电介质材料的沟槽形成，并且具有比基本阱更深的深度。 还提供了一种用于制造集成电路的方法，该集成电路包括用于存储电荷的半导体器件。

公开(公告)号：US07112461B2

公开(公告)日：2006-09-26

申请号：US10716249

申请日：2003-11-18

申请人： Olivier Menut ,  Yvon Gris

发明人： Olivier Menut ,  Yvon Gris

IPC分类号： H01L21/00

CPC分类号： H01L27/14603 ,  H01L27/1443 ,  H01L27/14643 ,  H01L31/03529 ,  Y02E10/50

摘要： An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

摘要翻译： 提供一种集成电路，其包括结合有具有p-n结的半导体光电二极管器件的衬底。 该光电二极管装置包括至少一个电容沟槽，该电容沟槽埋设在该衬底中，并与该结点并联连接。 在优选实施例中，衬底由硅形成，并且电容沟槽包括由绝缘壁部分包围的内部掺杂硅区域，该绝缘壁横向分离内部区域与衬底。 还提供了一种制造集成电路的方法，该集成电路包括具有p-n结的半导体光电二极管器件的衬底。

公开(公告)号：US06537873B2

公开(公告)日：2003-03-25

申请号：US10044812

申请日：2002-01-11

申请人： Olivier Menut ,  Yvon Gris

发明人： Olivier Menut ,  Yvon Gris

IPC分类号： H01L218242

CPC分类号： H01L27/10867 ,  H01L21/02667 ,  H01L21/2022 ,  H01L27/10832

摘要： The integrated circuit comprises a semiconductor substrate SB supporting a memory cell PM of the DRAM type comprising an access transistor T and a storage capacitor TRC. The access transistor is made on the substrate, and the substrate includes a capacitive trench TRC buried beneath the transistor and forming the storage capacitor, the capacitive trench being in contact with one of the source and drain regions of the transistor.

公开(公告)号：US20080012052A1

公开(公告)日：2008-01-17

申请号：US11687413

申请日：2007-03-16

申请人： Olivier Menut ,  Nicolas Planes ,  Sylvie Medico

发明人： Olivier Menut ,  Nicolas Planes ,  Sylvie Medico

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device includes a substrate of a first type of conductivity provided with at least one gate on one of its faces, and at least two doped regions of a second type of conductivity for forming a drain region and a source region. The two doped regions are arranged in the substrate flush with the face of the substrate on each side of a region of the substrate located under the gate for forming a channel between the drain and source regions. At least one region of doping agents of the second type of conductivity is implanted only in the channel.

摘要翻译： 一种半导体器件包括：第一类型导电体的衬底，其具有在其一个面上的至少一个栅极，以及用于形成漏极区域和源极区域的至少两个第二导电类型的掺杂区域。 两个掺杂区域布置在衬底中的衬底的面上与位于栅极下方的衬底的区域的每一侧齐平，以形成漏极和源极区域之间的沟道。 至少一个第二类导电性掺杂剂的区域仅植入通道中。