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    LOW POWER INSTRUCTION BUFFER FOR HIGH PERFORMANCE PROCESSORS
    1.
    发明申请
    LOW POWER INSTRUCTION BUFFER FOR HIGH PERFORMANCE PROCESSORS 审中-公开
    用于高性能处理器的低功耗指令缓冲器

    公开(公告)号：US20160055001A1

    公开(公告)日：2016-02-25

    申请号：US14463270

    申请日：2014-08-19

    申请人： Oracle International Corporation

    发明人： Gideon Levinsky ,  Jama Barreh ,  Jia Feng

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3879

    摘要： A method for operating an instruction buffer is disclosed. A read pointer that includes a value indicative of a given bank of a plurality of banks is received. A subset of the of the plurality of banks may then be selected dependent upon the read pointer and one or more control bits associated with an instruction stored at a location specified by the read pointer. The subset of the plurality of banks may then be activated, and an instruction read from each activated bank to form a dispatch group.

    摘要翻译： 公开了一种用于操作指令缓冲器的方法。 接收包括指示多个存储体的给定存储体的值的读指针。 然后可以根据读取指针和与存储在读取指针指定的位置处的指令相关联的一个或多个控制位来选择多个存储区中的一个子集。 然后可以激活多个存储体的子集，并且从每个激活的存储体读取指令以形成调度组。

    Power Reduction for Fully Associated Translation Lookaside Buffer
    3.
    发明申请
    Power Reduction for Fully Associated Translation Lookaside Buffer 有权
    完全相关的翻译后备缓冲区的功率降低

    公开(公告)号：US20150213153A1

    公开(公告)日：2015-07-30

    申请号：US14163096

    申请日：2014-01-24

    申请人： ORACLE INTERNATIONAL CORPORATION

    发明人： Manish Shah ,  Gideon Levinsky

    IPC分类号： G06F17/30 ,  G06F12/10 ,  G11C15/00

    CPC分类号： G06F17/30982 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2212/1028 ,  G06F2212/301 ,  G06F2212/684 ,  G11C15/00 ,  Y02D10/13

    摘要： An apparatus and method for saving power during TLB searches is disclosed. In one embodiment, a TLB includes a CAM having a plurality of entries each storing a virtual address, and enable logic coupled to the CAM. Responsive to initiation of a TLB query by a thread executing on a processor that includes the TLB, the enable logic is configured to enable only those CAM entries that are associated with the initiating thread. Entries in the CAM not associated with the thread are not enabled. Accordingly, an initial search of the TLB for responsive to the query is conducted only in the CAM entries that are associated with the thread. Those CAM entries that are not associated with the thread are not searched. As a result, dynamic power consumption during TLB searches may be reduced.

    摘要翻译： 公开了一种在TLB搜索中节省电力的装置和方法。 在一个实施例中，TLB包括具有多个条目的CAM，每个条目存储虚拟地址，并且使能耦合到CAM的逻辑。 响应于在包括TLB的处理器上执行的线程启动TLB查询，启用逻辑被配置为仅启用与启动线程相关联的那些CAM条目。 未与线程相关联的CAM中的条目未启用。 因此，仅在与线程相关联的CAM条目中进行用于响应于查询的TLB的初始搜索。 不搜索与线程无关的那些CAM条目。 因此，TLB搜索中的动态功耗可能会降低。

    Adaptive tablewalk translation storage buffer predictor
    4.
    发明授权
    Adaptive tablewalk translation storage buffer predictor 有权

    公开(公告)号：US10831675B2

    公开(公告)日：2020-11-10

    申请号：US16376773

    申请日：2019-04-05

    申请人： Oracle International Corporation

    发明人： John Pape ,  Manish Shah ,  Gideon Levinsky ,  Jared Smolens

    IPC分类号： G06F12/1045 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/1009 ,  G06N7/00 ,  G06F12/0817 ,  G06F12/1027

    摘要： A system for generating predictions for a hardware table walk to find a map of a given virtual address to a corresponding physical address is disclosed. The system includes a plurality of memories, which each includes respective plurality of entries, each of which includes a prediction of a particular one of a plurality of buffers which includes a portion of a virtual to physical address translation map. A first circuit may generate a plurality of hash values to retrieve a plurality of predictions from the plurality of memories, where each has value depends on a respective address and information associated with a respective thread. A second circuit may select a particular prediction of the retrieved predictions to use based on a history of previous predictions.

    Power reduction for fully associated translation lookaside buffer (TLB) and content addressable memory (CAM)
    5.
    发明授权
    Power reduction for fully associated translation lookaside buffer (TLB) and content addressable memory (CAM) 有权
    完全关联的翻译后备缓冲器（TLB）和内容可寻址存储器（CAM）的功耗降低

    公开(公告)号：US09208261B2

    公开(公告)日：2015-12-08

    申请号：US14163096

    申请日：2014-01-24

    申请人： Oracle International Corporation

    发明人： Manish Shah ,  Gideon Levinsky

    IPC分类号： G06F17/30 ,  G11C15/00 ,  G06F12/10

    CPC分类号： G06F17/30982 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2212/1028 ,  G06F2212/301 ,  G06F2212/684 ,  G11C15/00 ,  Y02D10/13

    摘要： An apparatus and method for saving power during TLB searches is disclosed. In one embodiment, a TLB includes a CAM having a plurality of entries each storing a virtual address, and enable logic coupled to the CAM. Responsive to initiation of a TLB query by a thread executing on a processor that includes the TLB, the enable logic is configured to enable only those CAM entries that are associated with the initiating thread. Entries in the CAM not associated with the thread are not enabled. Accordingly, an initial search of the TLB for responsive to the query is conducted only in the CAM entries that are associated with the thread. Those CAM entries that are not associated with the thread are not searched. As a result, dynamic power consumption during TLB searches may be reduced.

    摘要翻译： 公开了一种在TLB搜索中节省电力的装置和方法。 在一个实施例中，TLB包括具有多个条目的CAM，每个条目存储虚拟地址，并且使能耦合到CAM的逻辑。 响应于在包括TLB的处理器上执行的线程启动TLB查询，启用逻辑被配置为仅启用与启动线程相关联的那些CAM条目。 未与线程相关联的CAM中的条目未启用。 因此，仅在与线程相关联的CAM条目中进行用于响应于查询的TLB的初始搜索。 不搜索与线程无关的那些CAM条目。 因此，TLB搜索中的动态功耗可能会降低。

    Adaptive tablewalk translation storage buffer predictor
    7.
    发明授权
    Adaptive tablewalk translation storage buffer predictor 有权

    公开(公告)号：US10255197B2

    公开(公告)日：2019-04-09

    申请号：US15215027

    申请日：2016-07-20

    申请人： Oracle International Corporation

    发明人： John Pape ,  Manish Shah ,  Gideon Levinsky ,  Jared Smolens

    IPC分类号： G06F12/00 ,  G06F12/1045 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/1009 ,  G06N7/00

    摘要： A system for generating predictions for a hardware table walk to find a map of a given virtual address to a corresponding physical address is disclosed. The system includes a plurality memories, which each includes respective plurality of entries, each of which includes a prediction of a particular one of a plurality of buffers which includes a portion of a virtual to physical address translation map. A first circuit may generate a plurality of hash values to retrieve a plurality of predictions from the plurality of memories, where each has value depends on a respective address and information associated with a respective thread. A second circuit may select a particular prediction of the retrieved predictions to use based on a history of previous predictions.