-
公开(公告)号：US09672298B2
公开(公告)日：2017-06-06
申请号：US14267734
申请日：2014-05-01
Applicant: Oracle International Corporation
Inventor： Zoran Radovic , Jared C. Smolens , Robert T. Golla , Paul J. Jordan , Mark A. Luttrell
CPC classification number: G06F17/30985 , G06F9/30043 , G06F9/3834 , G06F9/3855 , G06F9/3859 , G06F11/08 , G06F17/30309 , G06F17/30507 , G06F17/30864
Abstract: Techniques for executing versioned memory access instructions. In one embodiment, a processor is configured to execute versioned store instructions of a first thread within a first mode of operation. In this embodiment, in the first mode of operation, the processor is configured to retire a versioned store instruction only after a version comparison has been performed for the versioned store instruction. In this embodiment the processor is configured to suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction until the oldest versioned store instruction has retired. In some embodiments, the processor is configured to execute versioned store instructions of a given thread within a second mode of operation, in which the processor is configured to retire outstanding versioned store instructions before a version comparison has been performed.
-
公开(公告)号：US20150046651A1
公开(公告)日：2015-02-12
申请号：US13961417
申请日：2013-08-07
Applicant: Oracle International Corporation
Inventor： Mark A. Luttrell
IPC: G06F12/08
CPC classification number: G06F12/084 , G06F12/0811 , G06F12/0864
Abstract: A processor may include a cache configured to store instructions and memory data for the processor. The cache may store instructions in which a relative address, such as for a branch instruction has been calculated, such that the instruction stored in the cache is modified from how the instruction is stored in main memory. The cache may include additional information in the tag to identify an instruction entry versus a memory data entry. When receiving a cache request, the cache may look at a type tag in addition to an address tag to determine if the request is a hit or a miss based upon the request being for an instruction from an instruction fetch unit or for memory data from a memory management unit. A cache entry may be invalidated and evicted if the address matches but the data type does not match.
Abstract translation: 处理器可以包括被配置为存储处理器的指令和存储器数据的高速缓存。 高速缓存可以存储其中已经计算了诸如用于分支指令的相对地址的指令，使得存储在高速缓存中的指令被修改为如何将指令存储在主存储器中。 高速缓存可以包括标签中的附加信息以识别指令条目与存储器数据条目。 当接收到缓存请求时，除了地址标签之外，高速缓存还可以查看类型标签，以根据来自指令获取单元的指令的请求或来自指令提取单元的存储器数据来确定请求是否是命中或未命中 内存管理单元。 如果地址匹配但数据类型不匹配，则缓存条目可能无效并被驱逐。
-
Patent Agency Ranking
公开(公告)号：US09367472B2
公开(公告)日：2016-06-14
申请号：US13914001
申请日：2013-06-10
Applicant: Oracle International Corporation
Inventor： William H. Bridge, Jr. , Paul Loewenstein , Mark A. Luttrell
CPC classification number: G06F12/0891 , G06F9/52 , G06F12/0804 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/084 , G06F12/0868
Abstract: Systems and methods for reliably using data storage media. Multiple processors are configured to access a persistent memory. For a given data block corresponding to a write access request from a first processor to the persistent memory, a cache controller prevents any read access of a copy of the given data block in an associated cache. The cache controller prevents any read access while detecting an acknowledgment that the given data block is stored in the persistent memory is not yet received. Until the acknowledgment is received, the cache controller allows write access of the copy of the given data block in the associated cache only for a thread in the first processor that originally sent the write access request. The cache controller invalidates any copy of the given data block in any cache levels below the associated cache.
Abstract translation: 可靠地使用数据存储介质的系统和方法。 多个处理器被配置为访问持久存储器。 对于对应于从第一处理器到持久存储器的写访问请求的给定数据块，高速缓存控制器防止在相关联的高速缓存中的给定数据块的副本的任何读访问。 高速缓存控制器在检测到尚未接收到持久存储器中存储给定数据块的确认时防止任何读访问。 在接收到确认之前，高速缓存控制器允许仅对最初发送写访问请求的第一处理器中的线程对相关联的高速缓存中的给定数据块的副本进行写访问。 高速缓存控制器使相关高速缓存下的任何缓存级别的给定数据块的任何副本无效。
-
公开(公告)号：US09940132B2
公开(公告)日：2018-04-10
申请号：US14967954
申请日：2015-12-14
Applicant: Oracle International Corporation
Inventor： Paul N. Loewenstein , Mark A. Luttrell , Paul J. Jordan
CPC classification number: G06F9/30043 , G06F9/3009 , G06F9/3851 , G06F11/0715 , G06F11/0757 , G06F11/3017 , G06F11/3471 , G06F12/084 , G06F2212/1008 , G06F2212/251 , Y02D10/34
Abstract: Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction.
-
公开(公告)号：US20160098274A1
公开(公告)日：2016-04-07
申请号：US14967954
申请日：2015-12-14
Applicant: Oracle International Corporation
Inventor： Paul N. Loewenstein , Mark A. Luttrell , Paul J. Jordan
CPC classification number: G06F9/30043 , G06F9/3009 , G06F9/3851 , G06F11/0715 , G06F11/0757 , G06F11/3017 , G06F11/3471 , G06F12/084 , G06F2212/1008 , G06F2212/251 , Y02D10/34
Abstract: Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction.
Abstract translation: 公开了关于在监视对指定的存储器位置的写入时暂停执行处理器线程的技术。 执行子系统可以被配置为执行加载指令，其使处理器从指定的存储器位置检索数据，并且原子地开始监视对指定位置的写入。 加载指令可以是加载监视器指令。 执行子系统还可以被配置为执行等待指令，该等待指令使处理器在由等待指令指定的间隔的至少一部分期间暂停处理器线程的执行，并且在间隔结束时继续执行处理器线程 。 等待指令可以是监视等待指令。 响应于检测到对由先前监视指令指定的存储器位置的写入，处理器还可被配置为恢复处理器线程的执行。
-
公开(公告)号：US20150317338A1
公开(公告)日：2015-11-05
申请号：US14267734
申请日：2014-05-01
Applicant: Oracle International Corporation
Inventor： Zoran Radovic , Jared C. Smolens , Robert T. Golla , Paul J. Jordan , Mark A. Luttrell
IPC: G06F17/30
CPC classification number: G06F17/30985 , G06F9/30043 , G06F9/3834 , G06F9/3855 , G06F9/3859 , G06F11/08 , G06F17/30309 , G06F17/30507 , G06F17/30864
Abstract: Techniques for executing versioned memory access instructions. In one embodiment, a processor is configured to execute versioned store instructions of a first thread within a first mode of operation. In this embodiment, in the first mode of operation, the processor is configured to retire a versioned store instruction only after a version comparison has been performed for the versioned store instruction. In this embodiment the processor is configured to suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction until the oldest versioned store instruction has retired. In some embodiments, the processor is configured to execute versioned store instructions of a given thread within a second mode of operation, in which the processor is configured to retire outstanding versioned store instructions before a version comparison has been performed.
Abstract translation: 用于执行版本化存储器访问指令的技术。 在一个实施例中，处理器被配置为在第一操作模式中执行第一线程的版本化存储指令。 在本实施例中，在第一操作模式中，处理器被配置为仅在版本化存储指令执行了版本比较之后才退出版本化存储指令。 在该实施例中，处理器被配置为抑制第一线程中比最旧的版本化存储指令更年轻的指令的退出，直到最旧的版本化存储指令已经退休。 在一些实施例中，处理器被配置为在第二操作模式中执行给定线程的版本化存储指令，其中处理器被配置为在执行版本比较之前退出未完成的版本化存储指令。
-
公开(公告)号：US20140365734A1
公开(公告)日：2014-12-11
申请号：US13914001
申请日：2013-06-10
Applicant: Oracle International Corporation
Inventor： William H. Bridge, JR. , Paul Loewenstein , Mark A. Luttrell
IPC: G06F12/08
CPC classification number: G06F12/0891 , G06F9/52 , G06F12/0804 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/084 , G06F12/0868
Abstract: Systems and methods for reliably using data storage media. Multiple processors are configured to access a persistent memory. For a given data block corresponding to a write access request from a first processor to the persistent memory, a cache controller prevents any read access of a copy of the given data block in an associated cache. The cache controller prevents any read access while detecting an acknowledgment that the given data block is stored in the persistent memory is not yet received. Until the acknowledgment is received, the cache controller allows write access of the copy of the given data block in the associated cache only for a thread in the first processor that originally sent the write access request. The cache controller invalidates any copy of the given data block in any cache levels below the associated cache.
Abstract translation: 可靠地使用数据存储介质的系统和方法。 多个处理器被配置为访问持久存储器。 对于对应于从第一处理器到持久存储器的写访问请求的给定数据块，高速缓存控制器防止在相关联的高速缓存中的给定数据块的副本的任何读访问。 高速缓存控制器在检测到尚未接收到持久存储器中存储给定数据块的确认时防止任何读访问。 在接收到确认之前，高速缓存控制器允许仅对最初发送写访问请求的第一处理器中的线程对相关联的高速缓存中的给定数据块的副本进行写访问。 高速缓存控制器使相关高速缓存下的任何缓存级别的给定数据块的任何副本无效。
-
-
-
-
-
-
Search Results
7
records
(took 0.018 seconds)
