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公开(公告)号：US09772375B2
公开(公告)日：2017-09-26
申请号：US14691332
申请日：2015-04-20
Applicant: Oracle International Corporation
Inventor： Sebastian Turullols , Vijay Srinivasan , Changku Hwang
CPC classification number: G01R31/31725 , G01R31/3004 , G01R31/31937 , G06F1/3206 , G06F1/3296 , H03K3/037 , H03K5/133 , H03K5/159
Abstract: Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit or digital voltage monitor circuit includes a coarse delay component or circuit that further delays the propagation of a clock signal through the delay line. The coarse delay circuit may be programmed to delay the propagation of the signal through the delay line in such a manner as to allow for multiple edges of a clock or test signal to travel simultaneously down the delay line and increase the sensitivity of the circuit. Additional sensitivity of the digital voltage monitor circuit may also be obtained through selection of the types of components that comprise the circuit and a clock jitter monitor circuit configured with a constant supply voltage.
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Patent Agency Ranking
公开(公告)号：US10296063B2
公开(公告)日：2019-05-21
申请号：US15474635
申请日：2017-03-30
Applicant: Oracle International Corporation
Inventor： Yifan YangGong , Sebastian Turullols , Vijay Srinivasan
IPC: G06F1/324 , G06F1/3206 , G06F1/3296
Abstract: An apparatus is disclosed, including a monitoring circuit, a translation circuit, a first filter circuit, a second filter circuit, and an interface. The monitoring circuit may be configured to receive a plurality of code values indicative of a voltage level of a power supply signal. The translation circuit may be configured to translate a particular code value to a corresponding voltage value of a plurality of voltage values. The first filter circuit may be configured to filter one or more of the plurality of voltage values to generate a plurality of filtered voltage values. The second filter circuit may be configured to generate a plurality of current values using one or more of the plurality of filtered voltage values and based on an impulse response of the power supply signal. The interface may be configured to send one or more of the plurality of current values to a functional circuit.
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公开(公告)号：US20180284867A1
公开(公告)日：2018-10-04
申请号：US15474635
申请日：2017-03-30
Applicant: Oracle International Corporation
Inventor： Yifan YangGong , Sebastian Turullols , Vijay Srinivasan
IPC: G06F1/32
CPC classification number: G06F1/3206 , G06F1/324 , G06F1/3296
Abstract: An apparatus is disclosed, including a monitoring circuit, a translation circuit, a first filter circuit, a second filter circuit, and an interface. The monitoring circuit may be configured to receive a plurality of code values indicative of a voltage level of a power supply signal. The translation circuit may be configured to translate a particular code value to a corresponding voltage value of a plurality of voltage values. The first filter circuit may be configured to filter one or more of the plurality of voltage values to generate a plurality of filtered voltage values. The second filter circuit may be configured to generate a plurality of current values using one or more of the plurality of filtered voltage values and based on an impulse response of the power supply signal. The interface may be configured to send one or more of the plurality of current values to a functional circuit.
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公开(公告)号：US09689917B2
公开(公告)日：2017-06-27
申请号：US14691352
申请日：2015-04-20
Applicant: Oracle International Corporation
Inventor： Sebastian Turullols , Vijay Srinivasan , Changku Hwang
CPC classification number: G01R31/31725 , G01R31/3004 , G01R31/31937 , G06F1/3206 , G06F1/3296 , H03K3/037 , H03K5/133 , H03K5/159
Abstract: Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit may include a clock jitter monitor circuit configured with a constant supply voltage. This clock jitter monitor is configured to measure the clock jitter that is experienced by the digital voltage monitor circuit and, when compared to measured voltage captured by the circuit, may be used to calibrate or otherwise correct the readings provided by the digital voltage monitor circuit.
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5.发明申请公开(公告)号：US20160033576A1
公开(公告)日：2016-02-04
申请号：US14691332
申请日：2015-04-20
Applicant: Oracle International Corporation
Inventor： Sebastian Turullols , Vijay Srinivasan , Changku Hwang
IPC: G01R31/317 , G01R19/25
CPC classification number: G01R31/31725 , G01R31/3004 , G01R31/31937 , G06F1/3206 , G06F1/3296 , H03K3/037 , H03K5/133 , H03K5/159
Abstract: Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit or digital voltage monitor circuit includes a coarse delay component or circuit that further delays the propagation of a clock signal through the delay line. The coarse delay circuit may be programmed to delay the propagation of the signal through the delay line in such a manner as to allow for multiple edges of a clock or test signal to travel simultaneously down the delay line and increase the sensitivity of the circuit. Additional sensitivity of the digital voltage monitor circuit may also be obtained through selection of the types of components that comprise the circuit and a clock jitter monitor circuit configured with a constant supply voltage.
Abstract translation: 本公开的实现涉及用于通过数字采样电路测量集成电路的片上电压电平的系统和/或方法。 特别地，系统和/或方法利用基于延迟线的模数 - 数字采样电路，其产生随时间的电压读数，例如在每个高频时钟周期。 在一个实施例中，数字采样电路或数字电压监视电路包括粗略延迟分量或电路，其进一步延迟时钟信号通过延迟线的传播。 粗延迟电路可以被编程为延迟信号通过延迟线的传播，以便允许时钟或测试信号的多个边沿同时沿着延迟线行进并且增加电路的灵敏度。 也可以通过选择构成电路的部件的类型和配置有恒定电源电压的时钟抖动监视电路来获得数字电压监视器电路的附加灵敏度。
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公开(公告)号：US20160034014A1
公开(公告)日：2016-02-04
申请号：US14691352
申请日：2015-04-20
Applicant: Oracle International Corporation
Inventor： Sebastian Turullols , Vijay Srinivasan , Changku Hwang
CPC classification number: G01R31/31725 , G01R31/3004 , G01R31/31937 , G06F1/3206 , G06F1/3296 , H03K3/037 , H03K5/133 , H03K5/159
Abstract: Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit may include a clock jitter monitor circuit configured with a constant supply voltage. This clock jitter monitor is configured to measure the clock jitter that is experienced by the digital voltage monitor circuit and, when compared to measured voltage captured by the circuit, may be used to calibrate or otherwise correct the readings provided by the digital voltage monitor circuit.
Abstract translation: 本公开的实现涉及用于通过数字采样电路测量集成电路的片上电压电平的系统和/或方法。 特别地，系统和/或方法利用基于延迟线的模数 - 数字采样电路，其产生随时间的电压读数，例如在每个高频时钟周期。 在一个实施例中，数字采样电路可以包括配置有恒定电源电压的时钟抖动监视电路。 该时钟抖动监视器被配置为测量数字电压监视器电路经历的时钟抖动，并且当与电路捕获的测量电压相比较时，可以使用它来校准或以其他方式校正由数字电压监视器电路提供的读数。
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