公开(公告)号：US5391921A

公开(公告)日：1995-02-21

申请号：US83322

申请日：1993-06-29

申请人： Osamu Kudoh ,  Kenji Okada ,  Hiroshi Shiba ,  Takuya Katoh

发明人： Osamu Kudoh ,  Kenji Okada ,  Hiroshi Shiba ,  Takuya Katoh

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002

摘要： A semiconductor device that has a feature in the spatial relationship between the wiring in a multi-level wiring and the intermediate insulating films. In the lower part of the second and/or subsequent levels of wiring there exist intermediate insulating films that have a pattern which is the same as the pattern of the wiring. Because of this arrangement, the intermediate insulating film does not exist between the wiring on the same level. The first structure of the multi-level wiring has the intermediate insulating films formed in wall-like shape, with the lower end of the intermediate insulating films reaching an underlying insulating layer formed on the surface of the semiconductor substrate. The second structure of the multi-level wiring is a quasi air gap metallization structure. As a result of realization of such structures, in the semiconductor device according to the present invention, the parasitic capacitance due to the coupling capacitances between the wiring can be reduced compared with a semiconductor device that has a structure in which the spaces between the wiring are filled with the intermediate films.

摘要翻译： 具有多层配线中的布线与中间绝缘膜之间的空间关系特征的半导体装置。 在第二和/或随后的布线层的下部存在具有与布线图案相同的图案的中间绝缘膜。 由于这种布置，中间绝缘膜不存在于同一层的布线之间。 多层布线的第一结构具有形成为壁状形状的中间绝缘膜，中间绝缘膜的下端到达形成在半导体基板的表面上的下面的绝缘层。 多层布线的第二结构是准气隙金属化结构。 作为实现这种结构的结果，在本发明的半导体器件中，与具有这样的结构的半导体器件相比，能够减少由于布线之间的耦合电容引起的寄生电容， 填充中间膜。

公开(公告)号：US06232620B1

公开(公告)日：2001-05-15

申请号：US09186285

申请日：1998-11-05

申请人： Takuya Katoh

发明人： Takuya Katoh

IPC分类号： H01L2900

CPC分类号： G02F1/1368

摘要： Active matrix TFT elements array in which the number of production steps is not increased and the high production yield can be achieved. A semiconductor film is formed by patterning in an elongated island shape between pixel electrodes disposed neighboring to each other in the direction of drain lines to provide a protrusion to prevent shorting across the pixel electrodes even if photoresist film residuals are produced.

摘要翻译： 活性矩阵TFT元件阵列，其中生产步骤的数量不增加并且可以实现高生产率。 通过在排列方向上彼此相邻设置的像素电极之间以细长的岛状形成半导体膜，以提供突起，以防止即使产生光致抗蚀剂膜残留物，也可以防止像素电极之间的短路。

公开(公告)号：US5952675A

公开(公告)日：1999-09-14

申请号：US861538

申请日：1997-05-22

申请人： Takuya Katoh

发明人： Takuya Katoh

IPC分类号： G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/04

CPC分类号： G02F1/136213 ,  H01L27/1214

摘要： Thin film transistor elements are disposed on a substrate in a matrix form. The thin film transistor element includes a source electrode, a drain electrode, isolated layer of a semiconductor layer and a gate insulating film, and a gate electrode. Drain wires and gate wires are provided on the substrate, and they are connected to the drain electrode and source electrode, respectively. Each of intersections of the drain wires and the gate wires has another isolated layer of a semiconductor layer and a gate insulating film. Each of the drain wires has an isolated conductive film which is made of the same material as the gate wires. The conductive film is formed to be contact with each of the drain wires so as to electrically support the drain wires each. Pixel electrodes are provided on the substrate. Each of the pixel electrodes preferably has a overlapping section with the adjacent gate wire and an auxiliary capacitor with another isolated layer of a semiconductor and a gate insulating film is formed on the overlapping section. Any leakage current do not flow between the thin film transistor elements in this thin film transistor elements array because the isolated layers including a semiconductor layer are provide in island form.

摘要翻译： 薄膜晶体管元件以矩阵形式设置在基板上。 薄膜晶体管元件包括源电极，漏电极，半导体层的隔离层和栅极绝缘膜，以及栅电极。 漏极导线和栅极线分别设置在基板上，分别与漏电极和源极连接。 漏极线和栅极线的每个交点具有半导体层和栅极绝缘膜的另一隔离层。 每个漏极线具有由与栅极线相同的材料制成的隔离导电膜。 导电膜形成为与每个漏极线接触，以便各排电线电连接。 像素电极设置在基板上。 每个像素电极优选地具有与相邻栅极线的重叠部分，并且在重叠部分上形成具有另一个半导体隔离层的辅助电容器和栅极绝缘膜。 由于包括半导体层的隔离层以岛形式提供，所以在该薄膜晶体管元件阵列中的薄膜晶体管元件之间不会有任何漏电流。

公开(公告)号：US5141896A

公开(公告)日：1992-08-25

申请号：US761568

申请日：1991-09-18

申请人： Takuya Katoh

发明人： Takuya Katoh

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L23/5226 ,  H01L23/5222 ,  H01L2924/0002

摘要： In a semiconductor device, an inter-level insulating film is formed at solid crossing points between upper level interconnections and lower-level interconnections, excepting via hole portions. This means that mechanical support between interconnection levels is given by solid crossing points between interconnections. For this, a semiconductor device having high durabilities against thermal and mechanical impacts can be obtained.Further, since inter-level regions other than the solid crossing points are made vacant to form a cavity, coupling capacity can be reduced to 1/3 to 1/2 of an ordinary multilevel interconnections wherein inter-level regions are fully filled with an inter-level insulating film.

公开(公告)号：US20080098788A1

公开(公告)日：2008-05-01

申请号：US11883012

申请日：2006-01-25

申请人： Takao Taniguchi ,  Shigeharu Ikeda ,  Minoru Hidaka ,  Takuya Katoh ,  Mitsuo Ueno

发明人： Takao Taniguchi ,  Shigeharu Ikeda ,  Minoru Hidaka ,  Takuya Katoh ,  Mitsuo Ueno

IPC分类号： B21D28/00

CPC分类号： B21D28/16

摘要： A press working apparatus is provided with a first working unit and a second working unit 14. In the first working unit, a first stage is performed for forming a half-blanked portion 15 with a projecting shape at a region where a through hole P is to be formed in a sheet W. In the second working unit 14, a second stage S2 is performed in which the half-blanked portion 15 is blanked from the sheet W by a second punch 26 and a second die 23. Also in the second stage S2, when a blanked body is blanked from the sheet W, shaving work is performed with respect to a side wall surface Pa on a region of the sheet W where the blanked body has been blanked.

摘要翻译： 冲压加工装置具有第一工作单元和第二工作单元14。 在第一工作单元中，执行第一阶段，以在片材W中形成通孔P的区域处形成具有突出形状的半冲切部分15.在第二工作单元14中，第二阶段 执行S 2，其中半冲切部分15通过第二冲头26和第二模具23从薄片W中冲切。 同样在第二阶段S 2中，当坯料坯料从坯料W中冲裁时，对已冲切坯料的薄片W的区域上的侧壁表面Pa进行切削加工。