公开(公告)号：US20140077979A1

公开(公告)日：2014-03-20

申请号：US14071195

申请日：2013-11-04

Applicant: Panasonic Corporation

Inventor： Takuji MIKI ,  Shiro SAKIYAMA ,  Naoshi YANAGISAWA

IPC: H03M1/10 ,  H03M1/46

CPC classification number: H03M1/1033 ,  H03M1/1061 ,  H03M1/466

Abstract: A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.

Abstract translation: 高阶DAC和低阶DAC各自具有多个具有以二进制比加权的电容值的电容元件，并且被配置为使得每个电容元件的第一端子连接到公共节点和第二端子 其选择性地连接到第一或第二电压。 高阶DAC和低阶DAC通过耦合电容耦合。 高阶DAC控制电路将逐次逼近电路输出的校正控制信号或数字信号选择性地输出到高阶DAC。 低阶DAC具有至少一个可变电容元件，其中第一端子连接到公共节点，并且第二端子选择性地连接到第一或第二电压，这取决于从第一或第二电压输出的数字信号的高位 高阶DAC的逐次逼近电路。

公开(公告)号：US20140062750A1

公开(公告)日：2014-03-06

申请号：US14073834

申请日：2013-11-06

Applicant: PANASONIC CORPORATION

Inventor： Takashi MORIE ,  Shiro SAKIYAMA ,  Naoshi YANAGISAWA ,  Toshiaki OZEKI ,  Takuji MIKI

IPC: H03M1/12 ,  G05F3/16

CPC classification number: H03M1/12 ,  G05F3/16

Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Abstract translation: 参考电压对于内部电路的干扰噪声和自噪声保持稳定。 用于稳定通过第一或第二信号线中的至少一个提供的参考电压的参考稳压器电路包括前级电路，其包括连接在第一和第二信号线之间的电容路径; 以及包括连接在第一和第二信号线之间的电阻路径的后级电路，以及在电容路径和电阻路径之间插入到提供参考电压的第一或第二信号线之一的电阻电路 。

公开(公告)号：US20130194719A1

公开(公告)日：2013-08-01

申请号：US13800800

申请日：2013-03-13

Applicant: PANASONIC CORPORATION

Inventor： Kazuo MATSUKAWA ,  Shiro SAKIYAMA ,  Naoshi YANAGISAWA

IPC: H01G4/38

CPC classification number: H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor array includes a plurality of comb capacitors sharing a common comb electrode. At least one of the comb capacitors has a comb electrode as a single base part. Each of the other ones of the comb capacitors has an electrode formed by coupling a plurality of base parts. In the other ones of the comb capacitors, a space between a wire coupling the base parts and an end of each of comb teeth of the common electrode, which is interposed between the base parts, is larger than a space between a base of each of the base parts of the plurality of comb capacitors and an end of each of the comb teeth of the common electrode, which is interposed between comb teeth of the base part.

Abstract translation: 电容器阵列包括共享共同梳电极的多个梳状电容器。 梳状电容器中的至少一个具有梳状电极作为单个基底部分。 梳状电容器中的每一个具有通过耦合多个基部而形成的电极。 在梳状电容器的另一个中，连接基部的电线与公共电极的每个梳齿之间的间隔在基座之间的空间大于基座之间的空间 多个梳状电容器的基部和公共电极的每个梳齿的端部插入在基部的梳齿之间。