公开(公告)号：US20140077979A1

公开(公告)日：2014-03-20

申请号：US14071195

申请日：2013-11-04

Applicant: Panasonic Corporation

Inventor： Takuji MIKI ,  Shiro SAKIYAMA ,  Naoshi YANAGISAWA

IPC: H03M1/10 ,  H03M1/46

CPC classification number: H03M1/1033 ,  H03M1/1061 ,  H03M1/466

Abstract: A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.

Abstract translation: 高阶DAC和低阶DAC各自具有多个具有以二进制比加权的电容值的电容元件，并且被配置为使得每个电容元件的第一端子连接到公共节点和第二端子 其选择性地连接到第一或第二电压。 高阶DAC和低阶DAC通过耦合电容耦合。 高阶DAC控制电路将逐次逼近电路输出的校正控制信号或数字信号选择性地输出到高阶DAC。 低阶DAC具有至少一个可变电容元件，其中第一端子连接到公共节点，并且第二端子选择性地连接到第一或第二电压，这取决于从第一或第二电压输出的数字信号的高位 高阶DAC的逐次逼近电路。

公开(公告)号：US20130154699A1

公开(公告)日：2013-06-20

申请号：US13724803

申请日：2012-12-21

Applicant: Panasonic Corporation

Inventor： Yusuke TOKUNAGA ,  Shiro SAKIYAMA

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03K4/501

Abstract: An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock.

Abstract translation: 响应于参考时钟的信号电平，第一振荡信号的信号电平和第二振荡信号的信号电平的转变，振荡器电路互补地增加或减小。 振荡控制电路将第一和第二振荡信号与比较电压进行比较，并根据比较结果转换参考时钟的信号电平。 参考控制电路增加或减小比较电压，使得与第一和第二振荡信号的相应摆动成比例的中间信号的信号电平与参考电压之间的差减小。 参考电压控制电路根据基准时钟和参考时钟之间的频率差增加或减小参考电压。

公开(公告)号：US20140285370A1

公开(公告)日：2014-09-25

申请号：US14300657

申请日：2014-06-10

Applicant: PANASONIC CORPORATION

Inventor： Takuji MIKI ,  Kazuo MATSUKAWA ,  Takashi MORIE ,  Shiro SAKIYAMA

IPC: H03M1/08 ,  H03M1/46

CPC classification number: H03M1/08 ,  H03M1/00 ,  H03M1/0641 ,  H03M1/12 ,  H03M1/466 ,  H03M1/468 ,  H03M1/804 ,  H03M3/30

Abstract: In a successive approximation AD converter, a noise generator outputs the output of a ΔΣ modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.

Abstract translation: 在逐次逼近AD转换器中，噪声发生器输出＆Dgr＆amp; 调制器作为噪声信号。 选择器电路可以代替用于产生下一位的比较目标电压的数字信号，将噪声信号输出到电容DAC的电容器元件。 在采样模拟输入电压时，噪声信号通过选择电路提供给电容DAC，之后执行正常的逐次逼近操作。

公开(公告)号：US20140062750A1

公开(公告)日：2014-03-06

申请号：US14073834

申请日：2013-11-06

Applicant: PANASONIC CORPORATION

Inventor： Takashi MORIE ,  Shiro SAKIYAMA ,  Naoshi YANAGISAWA ,  Toshiaki OZEKI ,  Takuji MIKI

IPC: H03M1/12 ,  G05F3/16

CPC classification number: H03M1/12 ,  G05F3/16

Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Abstract translation: 参考电压对于内部电路的干扰噪声和自噪声保持稳定。 用于稳定通过第一或第二信号线中的至少一个提供的参考电压的参考稳压器电路包括前级电路，其包括连接在第一和第二信号线之间的电容路径; 以及包括连接在第一和第二信号线之间的电阻路径的后级电路，以及在电容路径和电阻路径之间插入到提供参考电压的第一或第二信号线之一的电阻电路 。

公开(公告)号：US20130194719A1

公开(公告)日：2013-08-01

申请号：US13800800

申请日：2013-03-13

Applicant: PANASONIC CORPORATION

Inventor： Kazuo MATSUKAWA ,  Shiro SAKIYAMA ,  Naoshi YANAGISAWA

IPC: H01G4/38

CPC classification number: H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor array includes a plurality of comb capacitors sharing a common comb electrode. At least one of the comb capacitors has a comb electrode as a single base part. Each of the other ones of the comb capacitors has an electrode formed by coupling a plurality of base parts. In the other ones of the comb capacitors, a space between a wire coupling the base parts and an end of each of comb teeth of the common electrode, which is interposed between the base parts, is larger than a space between a base of each of the base parts of the plurality of comb capacitors and an end of each of the comb teeth of the common electrode, which is interposed between comb teeth of the base part.

Abstract translation: 电容器阵列包括共享共同梳电极的多个梳状电容器。 梳状电容器中的至少一个具有梳状电极作为单个基底部分。 梳状电容器中的每一个具有通过耦合多个基部而形成的电极。 在梳状电容器的另一个中，连接基部的电线与公共电极的每个梳齿之间的间隔在基座之间的空间大于基座之间的空间 多个梳状电容器的基部和公共电极的每个梳齿的端部插入在基部的梳齿之间。