公开(公告)号：US20140077979A1

公开(公告)日：2014-03-20

申请号：US14071195

申请日：2013-11-04

Applicant: Panasonic Corporation

Inventor： Takuji MIKI ,  Shiro SAKIYAMA ,  Naoshi YANAGISAWA

IPC: H03M1/10 ,  H03M1/46

CPC classification number: H03M1/1033 ,  H03M1/1061 ,  H03M1/466

Abstract: A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.

Abstract translation: 高阶DAC和低阶DAC各自具有多个具有以二进制比加权的电容值的电容元件，并且被配置为使得每个电容元件的第一端子连接到公共节点和第二端子 其选择性地连接到第一或第二电压。 高阶DAC和低阶DAC通过耦合电容耦合。 高阶DAC控制电路将逐次逼近电路输出的校正控制信号或数字信号选择性地输出到高阶DAC。 低阶DAC具有至少一个可变电容元件，其中第一端子连接到公共节点，并且第二端子选择性地连接到第一或第二电压，这取决于从第一或第二电压输出的数字信号的高位 高阶DAC的逐次逼近电路。

公开(公告)号：US20140285370A1

公开(公告)日：2014-09-25

申请号：US14300657

申请日：2014-06-10

Applicant: PANASONIC CORPORATION

Inventor： Takuji MIKI ,  Kazuo MATSUKAWA ,  Takashi MORIE ,  Shiro SAKIYAMA

IPC: H03M1/08 ,  H03M1/46

CPC classification number: H03M1/08 ,  H03M1/00 ,  H03M1/0641 ,  H03M1/12 ,  H03M1/466 ,  H03M1/468 ,  H03M1/804 ,  H03M3/30

Abstract: In a successive approximation AD converter, a noise generator outputs the output of a ΔΣ modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.

Abstract translation: 在逐次逼近AD转换器中，噪声发生器输出＆Dgr＆amp; 调制器作为噪声信号。 选择器电路可以代替用于产生下一位的比较目标电压的数字信号，将噪声信号输出到电容DAC的电容器元件。 在采样模拟输入电压时，噪声信号通过选择电路提供给电容DAC，之后执行正常的逐次逼近操作。

公开(公告)号：US20140062750A1

公开(公告)日：2014-03-06

申请号：US14073834

申请日：2013-11-06

Applicant: PANASONIC CORPORATION

Inventor： Takashi MORIE ,  Shiro SAKIYAMA ,  Naoshi YANAGISAWA ,  Toshiaki OZEKI ,  Takuji MIKI

IPC: H03M1/12 ,  G05F3/16

CPC classification number: H03M1/12 ,  G05F3/16

Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Abstract translation: 参考电压对于内部电路的干扰噪声和自噪声保持稳定。 用于稳定通过第一或第二信号线中的至少一个提供的参考电压的参考稳压器电路包括前级电路，其包括连接在第一和第二信号线之间的电容路径; 以及包括连接在第一和第二信号线之间的电阻路径的后级电路，以及在电容路径和电阻路径之间插入到提供参考电压的第一或第二信号线之一的电阻电路 。

公开(公告)号：US20140340250A1

公开(公告)日：2014-11-20

申请号：US14447315

申请日：2014-07-30

Applicant: PANASONIC CORPORATION

Inventor： Shiro DOSHO ,  Masao TAKAYAMA ,  Takuji MIKI

IPC: G06G7/184 ,  H03H19/00 ,  H03M3/02

CPC classification number: G06G7/184 ,  H03H19/004 ,  H03K3/0315 ,  H03M3/02

Abstract: A time integrator integrates time axis information represented by a phase difference between two signals. The time integrator includes a pulse generation circuit configured to convert a time difference between edges of two input signals to a difference between pulse widths of two pulse signals, and to output the two pulse signals, a load circuit having load characteristics changed by the two pulse signals, and an oscillation circuit coupled to the load circuit, and having an oscillation frequency changing in accordance with the load characteristics of the load circuit. An output of the oscillation circuit is output as a result of time integration.

Abstract translation: 时间积分器集成了由两个信号之间的相位差表示的时间轴信息。 时间积分器包括：脉冲发生电路，被配置为将两个输入信号的边沿之间的时间差转换为两个脉冲信号的脉冲宽度之间的差，并输出两个脉冲信号，具有由两个脉冲变化的负载特性的负载电路 信号和耦合到负载电路的振荡电路，并且根据负载电路的负载特性使振荡频率发生变化。 作为时间积分的结果输出振荡电路的输出。

公开(公告)号：US20130335251A1

公开(公告)日：2013-12-19

申请号：US13942478

申请日：2013-07-15

Applicant: Panasonic Corporation

Inventor： Shiro DOSHO ,  Masao TAKAYAMA ,  Takuji MIKI

IPC: H03M1/50

CPC classification number: H03M1/50 ,  G04F10/005

Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.

Abstract translation: 一种用于将两个输入信号之间的时间差转换成1位数字值并且调节两个输入信号之间的时间差以产生两个输出信号的时间 - 数字转换电路，包括：相位比较器，被配置为比较 两个输入信号彼此产生数字值; 相位选择器，被配置为输出具有前导相位的两个输入信号中的一个作为第一信号，并且具有滞后相位的两个输入信号中的另一个作为第二信号; 以及延迟单元，被配置为以延迟输出第一信号，其中时间 - 数字转换电路输出从延迟单元输出的信号和第二信号作为两个输出信号。

公开(公告)号：US20130154867A1

公开(公告)日：2013-06-20

申请号：US13770871

申请日：2013-02-19

Applicant: PANASONIC CORPORATION

Inventor： Shiro DOSHO ,  Masao TAKAYAMA ,  Takuji MIKI

IPC: H03M1/50

CPC classification number: H03M1/50 ,  H03M1/1215

Abstract: An A/D converter having high accuracy and high throughput irrespective of characteristic variations of analog circuits is provided. The A/D converter includes a voltage-to-time converter configured to synchronize with a sampling clock signal and convert an input analog voltage to a time difference between two signals, and a plurality of time-to-digital converters each configured to convert the time difference between the two signals to a digital value. The plurality of time-to-digital converters operate in an interleaved manner.

Abstract translation: 提供了与模拟电路的特性变化无关的具有高精度和高吞吐量的A / D转换器。 A / D转换器包括电压 - 时间转换器，其被配置为与采样时钟信号同步并将输入模拟电压转换为两个信号之间的时间差，并且多个时间 - 数字转换器被配置为将 两个信号之间的时差就是一个数字值。 多个时间 - 数字转换器以交错的方式工作。