公开(公告)号：US12001691B2

公开(公告)日：2024-06-04

申请号：US17702624

申请日：2022-03-23

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kazuhito Tanaka

IPC: G06F3/06 ,  G11C7/22

CPC classification number: G06F3/0622 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/222

Abstract: A memory controller controls access to a Synchronous Dynamic Random Access Memory (SDRAM) including banks. The memory controller includes: a receiver that receives a memory access request from an access master; a selector that selects one of a first issue mode and a second issue mode each related to command issuing; and an issuer that issues a command sequence to the SDRAM in response to the memory access request, in accordance with the one of the first issue mode and the second issue mode which is selected by the selector. The first issue mode is a mode in which an activation command for activating a bank among the banks is issued in continuous clock cycles without dividing the activation command, the activation command being included in the command sequence. The second issue mode is a mode in which the activation command is divided and issued in non-continuous clock cycles.

公开(公告)号：US11468961B2

公开(公告)日：2022-10-11

申请号：US16921255

申请日：2020-07-06

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Kazuhito Tanaka ,  Masaki Maeda

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/36 ,  G11C29/10

Abstract: A semiconductor memory device includes a data bus terminal group for outputting read data to an external device or inputting write data from an external device, a first terminal from or into which 1-bit data is output or input, a DBI circuit that executes a Data Bus Inversion (DBI) function, an error detection circuit that detects an internal error, and an information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group. The predetermined output information includes first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted, and second output information indicating whether or not an internal error has been detected by the error detection circuit.

公开(公告)号：US12026107B2

公开(公告)日：2024-07-02

申请号：US16923764

申请日：2020-07-08

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Kazuhito Tanaka

IPC: G11C7/22 ,  G06F1/04 ,  G06F13/16 ,  G11C7/10 ,  G11C8/18 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4096

Abstract: A command control system is provided which is configured to optimally set an output timing of a RAS command and an output timing of a CAS command for access requests different from each other. The command control system is configured to, when an output timing of a second RAS command is set in a first cycle time period which is a cycle starting from the reference time point, determine whether or not the second RAS command is output to a storage device in the first cycle time period in accordance with whether or not an output timing of a first CAS command is set in a second cycle time period constituted by a prescribed number of the cycles subsequent to the reference time point.