公开(公告)号：US20160380159A1

公开(公告)日：2016-12-29

申请号：US14753869

申请日：2015-06-29

Applicant: POINT ENGINEERING CO., LTD.

Inventor： Ki Myung NAM ,  Young Woon JEON ,  Kyoung Ja YUN

IPC: H01L33/48 ,  H01L33/54 ,  H01L33/62 ,  H01L33/58

CPC classification number: H01L33/486 ,  H01L33/44 ,  H01L33/483 ,  H01L33/54 ,  H01L33/58 ,  H01L33/62 ,  H01L2933/0025 ,  H01L2933/0033 ,  H01L2933/0066

Abstract: A chip substrate includes laminated conductive portions, and laminated insulation portions that electrically isolate the conductive portions, with a cavity in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate. The substrate includes an insulation layer on the upper surface, excluding a region of the cavity, and a continuous plating layer along a periphery of the chip substrate on the insulation layer. A portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer. A chip package includes a chip substrate, with an optical element sealed in the cavity by a sealing member or lens.

Abstract translation: 芯片基板包括层叠导电部分和层叠绝缘部分，其将导电部分与在芯片基板的上表面上包括绝缘部分的区域中的凹陷形状的腔体电隔离。 基板包括在上表面上的不包括空腔的区域的绝缘层，以及沿着绝缘层上的芯片基板的周边的连续镀层。 每个绝缘部分的顶表面的一部分暴露在空腔中，并且每个绝缘部分的顶表面的另一部分涂覆有绝缘层。 芯片封装包括芯片基板，光学元件通过密封构件或透镜密封在空腔中。