公开(公告)号：US20160380159A1

公开(公告)日：2016-12-29

申请号：US14753869

申请日：2015-06-29

Applicant: POINT ENGINEERING CO., LTD.

Inventor： Ki Myung NAM ,  Young Woon JEON ,  Kyoung Ja YUN

IPC: H01L33/48 ,  H01L33/54 ,  H01L33/62 ,  H01L33/58

CPC classification number: H01L33/486 ,  H01L33/44 ,  H01L33/483 ,  H01L33/54 ,  H01L33/58 ,  H01L33/62 ,  H01L2933/0025 ,  H01L2933/0033 ,  H01L2933/0066

Abstract: A chip substrate includes laminated conductive portions, and laminated insulation portions that electrically isolate the conductive portions, with a cavity in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate. The substrate includes an insulation layer on the upper surface, excluding a region of the cavity, and a continuous plating layer along a periphery of the chip substrate on the insulation layer. A portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer. A chip package includes a chip substrate, with an optical element sealed in the cavity by a sealing member or lens.

Abstract translation: 芯片基板包括层叠导电部分和层叠绝缘部分，其将导电部分与在芯片基板的上表面上包括绝缘部分的区域中的凹陷形状的腔体电隔离。 基板包括在上表面上的不包括空腔的区域的绝缘层，以及沿着绝缘层上的芯片基板的周边的连续镀层。 每个绝缘部分的顶表面的一部分暴露在空腔中，并且每个绝缘部分的顶表面的另一部分涂覆有绝缘层。 芯片封装包括芯片基板，光学元件通过密封构件或透镜密封在空腔中。

公开(公告)号：US20160380168A1

公开(公告)日：2016-12-29

申请号：US14753915

申请日：2015-06-29

Applicant: Point Engineering Co., Ltd.

Inventor： Sin Seok HAN ,  Soo Young CHOI ,  Ki Myung NAM

IPC: H01L33/58 ,  H05K1/02 ,  H05K1/03 ,  H01L33/48 ,  H01L33/62

CPC classification number: H01L33/58 ,  H01L33/44 ,  H01L33/486 ,  H01L33/62

Abstract: Disclosed is a chip substrate. The chip substrate includes: conductive portions laminated in one direction to constitute the chip substrate; insulation portions alternately laminated with the conductive portions to electrically isolate the conductive portions; a cavity formed at a predetermined depth in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate; and a groove portion disposed outside the cavity in a spaced-apart relationship with the cavity and formed at a predetermined depth in a recessed shape. According to the present invention, an adhesive agent is applied in a groove portion formed in advance. It is therefore possible to prevent the adhesive agent from being exposed to the light emitted from optical elements and to prevent the adhesive agent from being denatured. This makes it possible to enhance the reliability of lens bonding. Furthermore, there is no need to use an expensive resistant adhesive agent. An existing typical adhesive agent may be used as it is. This provides an effect of saving costs. Thus, there is an advantage in that a low-priced existing bonding material may be applied to a high-priced UV-C (deep-UV) package.

Abstract translation: 公开了一种芯片基板。 芯片基板包括：在一个方向上层叠以构成芯片基板的导电部分; 绝缘部分与导电部分交替地层叠以电绝缘导电部分; 在所述芯片基板的上表面的包含所述绝缘部的区域中形成为凹状的预定深度的空腔; 以及凹槽部分，以与空腔间隔开的关系设置在空腔外部，并以预定的凹陷形状形成。 根据本发明，在预先形成的槽部中涂布粘接剂。 因此，可以防止粘合剂暴露于从光学元件发出的光并防止粘合剂变性。 这使得可以提高透镜粘合的可靠性。 此外，不需要使用昂贵的耐热粘合剂。 可以直接使用现有的典型粘合剂。 这提供了节省成本的效果。 因此，优点在于低价格的现有粘合材料可以应用于高价位UV-C（深UV）封装。

公开(公告)号：US20160379957A1

公开(公告)日：2016-12-29

申请号：US14753807

申请日：2015-06-29

Applicant: POINT ENGINEERING CO., LTD.

Inventor： Bum Mo AHN ,  Ki Myung NAM ,  Seung Ho PARK

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/065 ,  H01L23/49811 ,  H01L23/49838 ,  H01L25/18 ,  H01L2225/06517 ,  H01L2225/06524

Abstract: Disclosed is a chip-mounting substrate. The chip-mounting substrate includes a plurality of conductive portions configured to apply voltages to at least two or more chips to be mounted, a plurality of insulation portions formed between the conductive portions and configured to electrically isolate the conductive portions, and a cavity formed in a region which includes at least three or more of the conductive portions and at least two or more of the insulation portions and depressed inward to form a space in which the chips are mounted.

Abstract translation: 公开了一种芯片安装基板。 芯片安装基板包括多个导电部分，其被配置为向要安装的至少两个或更多个芯片施加电压;多个绝缘部分，形成在导电部分之间并被构造成电绝缘导电部分;以及形成在 包括至少三个或更多个导电部分和至少两个或更多个绝缘部分并向内凹陷以形成其中安装芯片的空间的区域。