利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

115 条记录 (耗时 0.022 秒)

    Drive current improvement from recessed SiGe incorporation close to gate
    1.
    发明授权
    Drive current improvement from recessed SiGe incorporation close to gate 有权
    驱动目前从嵌入式SiGe并入门口的改进

    公开(公告)号：US07244654B2

    公开(公告)日：2007-07-17

    申请号：US10901568

    申请日：2004-07-29

    申请人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

    发明人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

    摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

    摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。

    Drive current improvement from recessed SiGe incorporation close to gate
    2.
    发明申请
    Drive current improvement from recessed SiGe incorporation close to gate 有权
    驱动目前从嵌入式SiGe并入门口的改进

    公开(公告)号：US20050139872A1

    公开(公告)日：2005-06-30

    申请号：US10901568

    申请日：2004-07-29

    申请人： Pr Chidambaram ,  Douglas Grider ,  Brian Smith ,  Haowen Bu ,  Lindsey Hall

    发明人： Pr Chidambaram ,  Douglas Grider ,  Brian Smith ,  Haowen Bu ,  Lindsey Hall

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/76

    CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

    摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

    摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。

    Increased drive current by isotropic recess etch
    3.
    发明申请
    Increased drive current by isotropic recess etch 有权
    通过各向同性凹槽蚀刻增加驱动电流

    公开(公告)号：US20060024898A1

    公开(公告)日：2006-02-02

    申请号：US10902360

    申请日：2004-07-29

    申请人： PR Chidambaram ,  Lindsey Hall ,  Haowen Bu

    发明人： PR Chidambaram ,  Lindsey Hall ,  Haowen Bu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636

    摘要： A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in the semiconductor body toward a channel portion of the semiconductor body underlying the gate structure. The method further includes epitaxially growing silicon (114) comprising stress-inducing species in the recesses. The source and drain regions are then implanted (120) in the semiconductor body on opposing sides of the gate structure.

    摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（108）并使用栅极结构作为蚀刻掩模使用各向同性蚀刻形成凹陷（112）。 各向同性蚀刻在半导体本体中形成凹槽，其在半导体本体中横向延伸到栅极结构下方的半导体主体的沟道部分。 该方法还包括在凹槽中外延生长包含应力诱导物质的硅（114）。 然后将源极和漏极区域（120）注入到栅极结构的相对侧上的半导体本体中。

    Transistor fabrication methods using dual sidewall spacers
    4.
    发明授权
    Transistor fabrication methods using dual sidewall spacers 有权
    使用双侧壁间隔件的晶体管制造方法

    公开(公告)号：US07217626B2

    公开(公告)日：2007-05-15

    申请号：US10899360

    申请日：2004-07-26

    申请人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar ,  Lindsey Hall

    发明人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar ,  Lindsey Hall

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after implanting the source/drain region (116), where the remaining sidewall spacer (120a) is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.

    摘要翻译： 呈现用于晶体管制造的方法（50），其中第一和第二侧壁间隔物（120a，120b）从栅极结构（114）横向向外形成，之后植入源极/漏极区（116）。 方法（50）还包括在注入源极/漏极区域（116）之后去除第二侧壁间隔物（120b）的全部或一部分，其中剩余侧壁间隔物（120a）在源极/漏极植入物之后更窄 改善源极/漏极接触电阻和PMD间隙填充，并促进晶体管沟道中的应力。

    Transistor fabrication methods using dual sidewall spacers
    6.
    发明申请
    Transistor fabrication methods using dual sidewall spacers 有权
    使用双侧壁间隔件的晶体管制造方法

    公开(公告)号：US20060019456A1

    公开(公告)日：2006-01-26

    申请号：US10899360

    申请日：2004-07-26

    申请人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar ,  Lindsey Hall

    发明人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar ,  Lindsey Hall

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after implanting the source/drain region (116), where the remaining sidewall spacer (120a) is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.

    摘要翻译： 呈现用于晶体管制造的方法（50），其中第一和第二侧壁间隔物（120a，120b）从栅极结构（114）横向向外形成，之后植入源极/漏极区（116）。 方法（50）还包括在注入源极/漏极区域（116）之后去除第二侧壁间隔物（120b）的全部或一部分，其中剩余侧壁间隔物（120a）在源极/漏极植入物之后更窄 改善源极/漏极接触电阻和PMD间隙填充，并促进晶体管沟道中的应力。

    Methods, systems and structures for forming improved transistors
    7.
    发明授权
    Methods, systems and structures for forming improved transistors 有权
    用于形成改进的晶体管的方法，系统和结构

    公开(公告)号：US07122435B2

    公开(公告)日：2006-10-17

    申请号：US10909515

    申请日：2004-08-02

    申请人： PR Chidambaram ,  Haowen Bu

    发明人： PR Chidambaram ,  Haowen Bu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Amorphous silicon regions are then formed (114) in the recesses. The amorphous silicon regions are re-crystallized. Sidewall spacers are formed (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The re-crystallized silicon regions formed in the recesses reside close to the transistor channel and serve to facilitate improved carrier mobility in NMOS type transistor devices.

    摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹部中形成非晶硅区域（114）。 非晶硅区域再结晶。 在门结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 形成在凹槽中的再结晶硅区域靠近晶体管沟道，并且有助于改善NMOS型晶体管器件中的载流子迁移率。

    Forming a retrograde well in a transistor to enhance performance of the transistor
    9.
    发明授权
    Forming a retrograde well in a transistor to enhance performance of the transistor 有权
    在晶体管中形成逆行阱以增强晶体管的性能

    公开(公告)号：US06927137B2

    公开(公告)日：2005-08-09

    申请号：US10725977

    申请日：2003-12-01

    申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Robert C. Bowen ,  Haowen Bu

    发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Robert C. Bowen ,  Haowen Bu

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/425 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/91

    摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

    摘要翻译： 提供了在晶体管中形成逆行阱的方法。 形成在基板和栅极之间具有基板，栅极和栅极氧化物层的晶体管结构。 衬底包括通常位于栅极下方的沟道区域。 将第一掺杂剂注入沟道区。 将第二掺杂剂注入到衬底中以形成掺杂源极区和掺杂漏极区。 将第三掺杂剂注入到栅极氧化物层中。 进行源极/漏极退火以分别在掺杂源极区域和掺杂漏极区域中形成源极和漏极。 源极/漏极退火使得沟道区域中的第一掺杂剂的一部分被第三掺杂剂吸引到栅极氧化物层中。