公开(公告)号：US20050118792A1

公开(公告)日：2005-06-02

申请号：US10725977

申请日：2003-12-01

申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Robert Bowen ,  Haowen Bu

发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Robert Bowen ,  Haowen Bu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/425 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/91

摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

公开(公告)号：US07670892B2

公开(公告)日：2010-03-02

申请号：US11268040

申请日：2005-11-07

申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas T. Grider

发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas T. Grider

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。 由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。

公开(公告)号：US06927137B2

公开(公告)日：2005-08-09

申请号：US10725977

申请日：2003-12-01

申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Robert C. Bowen ,  Haowen Bu

发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Robert C. Bowen ,  Haowen Bu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/425 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/91

摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

摘要翻译： 提供了在晶体管中形成逆行阱的方法。 形成在基板和栅极之间具有基板，栅极和栅极氧化物层的晶体管结构。 衬底包括通常位于栅极下方的沟道区域。 将第一掺杂剂注入沟道区。 将第二掺杂剂注入到衬底中以形成掺杂源极区和掺杂漏极区。 将第三掺杂剂注入到栅极氧化物层中。 进行源极/漏极退火以分别在掺杂源极区域和掺杂漏极区域中形成源极和漏极。 源极/漏极退火使得沟道区域中的第一掺杂剂的一部分被第三掺杂剂吸引到栅极氧化物层中。

公开(公告)号：US20070105294A1

公开(公告)日：2007-05-10

申请号：US11268040

申请日：2005-11-07

申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas Grider

发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas Grider

IPC分类号： H01L21/8234

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。 由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。

公开(公告)号：US07061058B2

公开(公告)日：2006-06-13

申请号：US11148805

申请日：2005-06-09

申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Robert C. Bowen ,  Haowen Bu

发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Robert C. Bowen ,  Haowen Bu

IPC分类号： H01L29/10

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/91

摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

摘要翻译： 提供了在晶体管中形成逆行阱的方法。 形成在基板和栅极之间具有基板，栅极和栅极氧化物层的晶体管结构。 衬底包括通常位于栅极下方的沟道区域。 将第一掺杂剂注入沟道区。 将第二掺杂剂注入到衬底中以形成掺杂源极区和掺杂漏极区。 将第三掺杂剂注入到栅极氧化物层中。 进行源极/漏极退火以分别在掺杂源极区域和掺杂漏极区域中形成源极和漏极。 源极/漏极退火使得沟道区域中的第一掺杂剂的一部分被第三掺杂剂吸引到栅极氧化物层中。

公开(公告)号：US20060068541A1

公开(公告)日：2006-03-30

申请号：US10950138

申请日：2004-09-24

申请人： PR Chidambaram ,  Srinivasan Chakravarthi ,  Haowen Bu ,  Rajesh Khamankar

发明人： PR Chidambaram ,  Srinivasan Chakravarthi ,  Haowen Bu ,  Rajesh Khamankar

IPC分类号： H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown poly oxide layer (212). Offset spacers are formed adjacent to sidewalls of the gate electrodes (216). Extension regions are then formed (214) within the PMOS region and the NMOS region. Sidewall spacers are formed (218) adjacent to the sidewalls of the gate. electrodes. An n-type dopant is implanted into the NMOS region to form source/drain regions and a p-type dopant is implanted with an overdose amount into the PMOS region to form the source/drain regions within the PMOS region (220). A poly cap layer is formed over the device (222) and an anneal or other thermal process is performed (224) that causes the p-type dopant to diffuse into the nitride containing cap oxide layer and obtain a selected dopant profile having sufficient lateral abruptness.

摘要翻译： 公开了制造半导体器件的方法（200）。 在半导体主体上的栅电极（210）上形成多个氧化物层，以及在PMOS和NMOS区域内限定在半导体本体内的有源区。 在生长的多晶氧化物层（212）上形成含氮化物的氧化物层。 邻近栅电极（216）的侧壁形成偏移间隔物。 然后在PMOS区域和NMOS区域内形成延伸区域（214）。 侧壁间隔件形成（218）邻近门的侧壁。 电极。 将n型掺杂剂注入到NMOS区域中以形成源极/漏极区域，并且将过量剂量的p型掺杂剂注入到PMOS区域中以在PMOS区域（220）内形成源极/漏极区域。 在器件（222）之上形成多晶硅层，并执行退火或其它热处理（224），使得p型掺杂剂扩散到含氮化物的氧化物层中，并获得具有足够横向突变性的选定掺杂剂分布 。

公开(公告)号：US20050224874A1

公开(公告)日：2005-10-13

申请号：US11148805

申请日：2005-06-09

申请人： Srinivasan Chakravarthi ,  Pr Chrdambaram ,  Robert Bowen ,  Haowen Bu

发明人： Srinivasan Chakravarthi ,  Pr Chrdambaram ,  Robert Bowen ,  Haowen Bu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/425 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/91

摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

公开(公告)号：US07244654B2

公开(公告)日：2007-07-17

申请号：US10901568

申请日：2004-07-29

申请人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

发明人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。

公开(公告)号：US07122435B2

公开(公告)日：2006-10-17

申请号：US10909515

申请日：2004-08-02

申请人： PR Chidambaram ,  Haowen Bu

发明人： PR Chidambaram ,  Haowen Bu

IPC分类号： H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Amorphous silicon regions are then formed (114) in the recesses. The amorphous silicon regions are re-crystallized. Sidewall spacers are formed (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The re-crystallized silicon regions formed in the recesses reside close to the transistor channel and serve to facilitate improved carrier mobility in NMOS type transistor devices.

摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹部中形成非晶硅区域（114）。 非晶硅区域再结晶。 在门结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 形成在凹槽中的再结晶硅区域靠近晶体管沟道，并且有助于改善NMOS型晶体管器件中的载流子迁移率。

公开(公告)号：US20050139872A1

公开(公告)日：2005-06-30

申请号：US10901568

申请日：2004-07-29

申请人： Pr Chidambaram ,  Douglas Grider ,  Brian Smith ,  Haowen Bu ,  Lindsey Hall

发明人： Pr Chidambaram ,  Douglas Grider ,  Brian Smith ,  Haowen Bu ,  Lindsey Hall

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。