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12 条记录 (耗时 0.01 秒)

    Drive current improvement from recessed SiGe incorporation close to gate
    2.
    发明申请
    Drive current improvement from recessed SiGe incorporation close to gate 有权
    驱动目前从嵌入式SiGe并入门口的改进

    公开(公告)号：US20050139872A1

    公开(公告)日：2005-06-30

    申请号：US10901568

    申请日：2004-07-29

    申请人： Pr Chidambaram ,  Douglas Grider ,  Brian Smith ,  Haowen Bu ,  Lindsey Hall

    发明人： Pr Chidambaram ,  Douglas Grider ,  Brian Smith ,  Haowen Bu ,  Lindsey Hall

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/76

    CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

    摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

    摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。

    Stacked/composite gate dielectric which incorporates nitrogen at an interface
    3.
    发明授权
    Stacked/composite gate dielectric which incorporates nitrogen at an interface 有权
    在界面上结合氮的堆叠/复合栅极电介质

    公开(公告)号：US06323114B1

    公开(公告)日：2001-11-27

    申请号：US09447407

    申请日：1999-11-22

    申请人： Sunil V. Hattangady ,  Tad (Douglas) Grider ,  John W. Kuehne

    发明人： Sunil V. Hattangady ,  Tad (Douglas) Grider ,  John W. Kuehne

    IPC分类号： H01L213205

    CPC分类号： H01L21/28202 ,  H01L21/32105 ,  H01L29/513 ,  H01L29/518

    摘要： An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate which includes a dielectric layer formed between a first structure and a second structure, the method comprising the steps of: growing an oxide-containing layer (layer 204 of FIGS. 2a-2d) on the first structure (substrate 202 of FIGS. 2a-2d); forming a silicon-containing layer (layer 206 of FIG. 2b) on the oxide-containing layer; oxidizing substantially all of the silicon-containing layer by subjecting it to an ambient comprised of oxygen and nitrogen with a substrate temperature around 700 to 800 C.; and forming the second structure (layer 214 of FIG. 2d) on the oxidized silicon-containing layer. Preferably, the step of oxidizing substantially all of the silicon-containing layer is performed by subjecting the silicon-containing layer to an ambient containing: N2O with a wafer temperature around 700 to 800 C.; or NO with a wafer temperature around 700 to 800 C. The nitrogen is, preferably, incorporated between the oxide-containing layer and the first structure and/or between the oxide-containing layer and the oxidized silicon-containing layer.

    摘要翻译： 本发明的一个实施例是一种在半导体衬底上制造电子器件的方法，该半导体衬底包括在第一结构和第二结构之间形成的介电层，该方法包括以下步骤：生长含氧化物层（层204 图2a-2d）在第一结构（图2a-2d的基板202）上; 在含氧化物层上形成含硅层（图2b的层206）; 通过使其包含氧和氮的环境基本上全部氧化，衬底温度约为700至800℃; 并在氧化的含硅层上形成第二结构（图2d的层214）。 优选地，基本上氧化所述含硅层的步骤通过使含硅层在约700至800℃的晶片温度下经受含有N 2 O的环境来进行; 或NO，晶片温度约为700至800℃。氮优选并入含氧化物层和第一结构之间和/或含氧化物层和氧化含硅层之间。

    High performance CMOS transistors using PMD liner stress
    4.
    发明申请
    High performance CMOS transistors using PMD liner stress 有权
    使用PMD衬垫应力的高性能CMOS晶体管

    公开(公告)号：US20070128806A1

    公开(公告)日：2007-06-07

    申请号：US11670192

    申请日：2007-02-01

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

    摘要： A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

    摘要翻译： 在晶体管栅极（40）和源极和漏极区域（70）之上形成硝酸氧化物层（110）。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

    High performance CMOS transistors using PMD linear stress
    5.
    发明申请
    High performance CMOS transistors using PMD linear stress 有权
    使用PMD线性应力的高性能CMOS晶体管

    公开(公告)号：US20050245012A1

    公开(公告)日：2005-11-03

    申请号：US10833419

    申请日：2004-04-28

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

    IPC分类号： H01L21/336 ,  H01L23/58 ,  H01L29/78

    CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

    摘要： A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

    摘要翻译： 氮化硅层（110）形成在晶体管栅极（40）和源极和漏极区域（70）之上。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

    PMD liner nitride films and fabrication methods for improved NMOS performance
    6.
    发明申请
    PMD liner nitride films and fabrication methods for improved NMOS performance 有权
    PMD衬垫氮化物膜和用于改善NMOS性能的制造方法

    公开(公告)号：US20050233514A1

    公开(公告)日：2005-10-20

    申请号：US10827692

    申请日：2004-04-19

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

    IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/823807 ,  H01L29/665 ,  Y10S438/938

    摘要： Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.

    摘要翻译： 提供半导体器件（102）和制造方法（10），其中在NMOS晶体管上形成氮化物膜（130）以在NMOS晶体管的全部或一部分中施加拉伸应力以改善载流子迁移率。 氮化物层（130）最初以高氢含量在低温下沉积在晶体管上，以在后端处理之前在半导体本体中提供适度的拉伸应力。 随后的后端热处理降低了膜的氢含量并且引起所施加的拉伸应力的增加。

    Selective germanium deposition on silicon and resulting structures
    9.
    发明授权
    Selective germanium deposition on silicon and resulting structures 失效
    选择性锗在硅上沉积并产生结构

    公开(公告)号：US5089872A

    公开(公告)日：1992-02-18

    申请号：US515589

    申请日：1990-04-27

    申请人： Mehmet Ozturk ,  Jimmie Wortman ,  Douglas Grider

    发明人： Mehmet Ozturk ,  Jimmie Wortman ,  Douglas Grider

    IPC分类号： H01L21/285 ,  H01L29/423 ,  H01L29/45

    CPC分类号： H01L29/456 ,  H01L21/28525 ,  H01L29/41783 ,  H01L29/78 ,  H01L2924/0002

    摘要： The invention is a method of selectively forming contacts on ultra shallow source and drain junctions. The method comprises forming a gate structure that defines a gate on a silicon substrate, portions of which are covered with a layer of silicon dioxide while the portions adjacent the gate form a silicon surface. The gate structure includes a surface material upon which germanium will not deposit at a temperature that is otherwise high enough to cause germanium to deposit from a germanium containing gas onto a silicon surface, but that is lower than the temperature at which germanium will deposit on the gate surface material. A source and drain are formed in the silicon substrate in the portions adjacent the gate by adding dopant atoms and in which the source and drain are separated by an active region of the silicon substrate defined by the gate structure. The substrate is then exposed to a germanium containing gas at a temperature high enough to cause the germanium to deposit from the germanium containing gas into the silicon surface but lower than the temperature at which the germanium will deposit on the gate structure surface material. The result is self-aligned germanium contacts to the source and the drain. The method can further comprise selectively depositing a metal on the germanium and annealing the deposit to form a germanide compound from the reaction between the deposited germanium and the deposited metal.

    摘要翻译： 本发明是在超浅源极和漏极结上选择性地形成接触的方法。 该方法包括形成限定硅衬底上的栅极的栅极结构，其一部分被二氧化硅层覆盖，而与栅极相邻的部分形成硅表面。 栅极结构包括表面材料，锗不会在其上高度足够沉积以使锗从含锗气体沉积到硅表面上的温度沉积，但是低于锗沉积在硅表面上的温度 门表面材料。 源极和漏极通过添加掺杂剂原子在与栅极相邻的部分中的硅衬底中形成，其中源极和漏极由栅极结构限定的硅衬底的有源区域分开。 然后将衬底在足够高的温度下暴露于含锗气体，以使锗从含锗气体沉积到硅表面中，但低于锗将沉积在栅极结构表面材料上的温度。 结果是自对准的锗接触源和漏极。 该方法还可以包括选择性地在锗上沉积金属并退火沉积物以从沉积的锗和沉积的金属之间的反应形成锗化合物。

    Nitrogen based implants for defect reduction in strained silicon
    10.
    发明申请
    Nitrogen based implants for defect reduction in strained silicon 有权
    用于应变硅缺陷还原的氮基植入物

    公开(公告)号：US20070105294A1

    公开(公告)日：2007-05-10

    申请号：US11268040

    申请日：2005-11-07

    申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas Grider

    发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas Grider

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

    摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

    摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。 由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。