公开(公告)号：US5583705A

公开(公告)日：1996-12-10

申请号：US560084

申请日：1995-11-17

申请人： Pablo A. Ziperovich ,  Xiaodong Che

发明人： Pablo A. Ziperovich ,  Xiaodong Che

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B27/36

CPC分类号： G11B20/10194 ,  G11B20/10055 ,  G11B27/36 ,  G11B20/1258

摘要： Write precomposition optimization for a partial response maximum likelihood ("PRME") magnetic recording chapel adapted to a mass production environment. Optimal write precompensation may be determined by writing a tribit data pattern known to produce worst case nonlinear transition shift ("NLTS") onto a magnetic recording medium; reading back the recorded data pattern; and calculating the mean-squared error ("MSE") for one or more of the equalized data sample levels associated with the PRML channel to be optimized. The writing and reading back process is repeated with varying amounts of precompensation applied to the written pattern. The optimal amount of write precompensation is determined eider by minimizing the MSE for a selected sample level or by minimizing MSE between the middle and the upper or lower of the ternary PRML sample levels.

摘要翻译： 为适应于大规模生产环境的部分响应最大似然（“PRME”）磁记录教堂编写预组合优化。 可以通过将已知产生最坏情况非线性转变位移（“NLTS”）的三位数据模式写入到磁记录介质上来确定最佳写预补偿; 读回记录数据模式; 以及计算与要优化的PRML信道相关联的一个或多个均衡数据样本水平的均方误差（“MSE”）。 重复写入和回读过程，并对写入的图案应用不同量的预补偿。 通过最小化所选样本级别的MSE或通过使三进制PRML样本级别的中间和更高或更低之间的MSE最小化来确定写入预补偿的最佳量。

公开(公告)号：US5493454A

公开(公告)日：1996-02-20

申请号：US317902

申请日：1994-10-04

申请人： Pablo A. Ziperovich ,  Xiaodong Che

发明人： Pablo A. Ziperovich ,  Xiaodong Che

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B27/36

CPC分类号： G11B20/10194 ,  G11B20/10055 ,  G11B27/36 ,  G11B20/1258

摘要： Write precompensation optimization for a partial response maximum likelihood ("PRML") magnetic recording channel adapted to a mass production environment. Optimal write precompensation may be determined by writing a tribit data pattern known to produce worst case nonlinear transition shift ("NLTS") onto a magnetic recording medium; reading back the recorded data pattern; and calculating the mean-squared error ("MSE") for one or more of the equalized data sample levels associated with the PRML channel to be optimized. The writing and reading back process is repeated with varying amounts of precompensation applied to the written pattern. The optimal amount of write precompensation is determined either by minimizing the MSE for a selected sample level or by minimizing MSE between the middle and the upper or lower of the ternary PRML sample levels.

摘要翻译： 为适应于大规模生产环境的部分响应最大似然（“PRML”）磁记录通道编写预补偿优化。 可以通过将已知产生最坏情况非线性转变位移（“NLTS”）的三位数据模式写入到磁记录介质上来确定最佳写预补偿; 读回记录数据模式; 以及计算与要优化的PRML信道相关联的一个或多个均衡数据样本水平的均方误差（“MSE”）。 重复写入和回读过程，并对写入的图案应用不同量的预补偿。 通过最小化所选样本级别的MSE或通过使三进制PRML样本级别的中间和上限或更低之间的MSE最小化来确定写入预补偿的最佳量。

公开(公告)号：US6025965A

公开(公告)日：2000-02-15

申请号：US266044

申请日：1999-03-10

申请人： Pablo A. Ziperovich

发明人： Pablo A. Ziperovich

IPC分类号： G11B5/02 ,  G11B5/09

CPC分类号： G11B5/02 ,  G11B5/09

摘要： A power-reduced digital control within a feedback control loop of a sampling data detection channel controls a predetermined operating parameter of the channel in which an analog to digital converter provides digital samples of information in the channel at a predetermined channel clock rate. The digital control comprises a parameter error extraction circuit clocked at the predetermined channel rate which is connected to receive digital samples from the analog to digital converter, and which extracts parameter error values from the digital samples; an averaging circuit for averaging the extracted parameter error values over an integral submultiple of the predetermined channel clock rate; and a parameter error processing circuit which is connected to the parameter error extraction circuit and clocked at the integral submultiple of the predetermined channel rate for generating and putting out digital control values within the feedback control loop for controlling the predetermined operating parameter. The parameter may be timing, gain or DC offset, and the sampling data detection channel may be a PRML channel of a magnetic hard disk drive. A power-reduced control method is also described.

摘要翻译： 采样数据检测通道的反馈控制回路内的功率降低的数字控制控制通道的预定操作参数，其中模数转换器以预定的通道时钟速率在信道中提供信息的数字采样。 数字控制包括以预定信道速率时钟的参数误差提取电路，其被连接以从模数转换器接收数字样本，并从数字样本中提取参数误差值; 平均电路，用于对所提取的参数误差值在所述预定信道时钟速率的整数倍数上进行平均; 以及参数误差处理电路，其连接到参数误差提取电路，并以预定信道速率的积分微分计时，以产生并输出用于控制预定操作参数的反馈控制回路内的数字控制值。 该参数可以是定时，增益或DC偏移，并且采样数据检测通道可以是磁性硬盘驱动器的PRML通道。 还描述了功率降低控制方法。

公开(公告)号：US5737342A

公开(公告)日：1998-04-07

申请号：US656021

申请日：1996-05-31

申请人： Pablo A. Ziperovich

发明人： Pablo A. Ziperovich

IPC分类号： G01R31/316 ,  G01R31/28 ,  G01R31/3185 ,  G11B20/10 ,  G11B20/18

CPC分类号： G11B20/10055 ,  G01R31/318516 ,  G11B20/10037 ,  G11B20/182 ,  G11B20/10009

摘要： An on-chip self-test circuit for testing digital elements of a synchronous sampling data detection channel chip, such as a PRML channel of a hard disk drive, with digital pseudo samples representative of samples coming from an analog channel section, includes a sample generator generating idealized digital pseudo samples in accordance with a predetermined spectrum response, a digital noise generator generating digital noise values, a first combining circuit combining the idealized digital pseudo samples with the digital noise values to produce noisy pseudo samples, a bias injection circuit connected to the sample generator and adding a predetermined bias to the idealized digital pseudo samples to produce biased pseudo samples, and a second combining circuit for combining the noisy pseudo samples with the biased pseudo samples to put out biased noisy pseudo samples to test digital data processing and channel control elements of the channel chip.

摘要翻译： 用于测试表示来自模拟通道部分的样本的数字伪样本的同步采样数据检测通道芯片（例如硬盘驱动器的PRML通道）的数字元件的片上自检电路包括采样发生器 根据预定的频谱响应生成理想化的数字伪样本，产生数字噪声值的数字噪声发生器，将理想数字伪样本与数字噪声值组合的第一组合电路，产生有噪声的伪样本;偏置注入电路 并将预定偏置加到理想化的数字伪样本以产生偏置的伪样本;以及第二组合电路，用于将噪声伪样本与偏置的伪样本组合，以推出偏置噪声伪样本，以测试数字数据处理和信道控制 通道芯片的元件。

公开(公告)号：US5258940A

公开(公告)日：1993-11-02

申请号：US851817

申请日：1992-03-16

申请人： Jonathan D. Coker ,  Richard L. Galbraith ,  Pablo A. Ziperovich

发明人： Jonathan D. Coker ,  Richard L. Galbraith ,  Pablo A. Ziperovich

IPC分类号： G11B5/09 ,  H03H17/06 ,  H03H21/00 ,  G06F15/31

CPC分类号： H03H17/06

摘要： A 10-tap finite impulse response (FIR) digital filter is provided in a partial response signaling and maximum-likelihood (PRML) data channel. A plurality of partial sums of predetermined tap weights are stored in a palette random access memory (RAM). A fixed qualifier value is received and used together with selected ones of the stored partial sums for calculating a predetermined tap weight. Predetermined filter coefficients are calculated and stored in a filter RAM using the calculated predetermined tap weight and predefined ones of the stored partial sums.

摘要翻译： 在部分响应信令和最大似然（PRML）数据信道中提供10抽头有限脉冲响应（FIR）数字滤波器。 多个预定抽头权重的部分和存储在调色板随机存取存储器（RAM）中。 接收固定的限定符值并与所选存储的部分和一起使用以用于计算预定抽头权重。 使用计算的预定抽头权重和存储的部分和的预定义的抽头权重来计算预定的滤波器系数并将其存储在滤波器RAM中。

公开(公告)号：US5552942A

公开(公告)日：1996-09-03

申请号：US295505

申请日：1994-08-23

申请人： Pablo A. Ziperovich ,  James Chiao

发明人： Pablo A. Ziperovich ,  James Chiao

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  H04L7/033 ,  H04L7/04 ,  H04L7/10 ,  G11B5/09 ,  H03D3/24 ,  H04L25/38

CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/1403 ,  G11B20/1258 ,  H04L7/0337 ,  H04L7/042 ,  H04L7/10

摘要： A "zero phase start" optimization circuit for a Partial Response, Maximum Likelihood ("PRML") data channel dynamically determines a more optimal starting phase for the timing recovery process in a synchronous communication or storage system. The disclosed circuit includes a quantizer, a summing junction, either an absolute value or squaring function, and an integrator. A firmware based optimization routine causes a timing control loop to go through a series of timing acquisition modes, each time starting a clocking oscillator at different phase. The optimization circuit calculates the mean squared error between actual and expected sample values from a known frequency preamble pattern for each timing acquisition. The minimum MSE value corresponds to a more optimal starting phase for the timing control loop oscillator.

摘要翻译： 用于部分响应，最大似然（“PRML”）数据信道的“零相位起始”优化电路动态地确定用于同步通信或存储系统中的定时恢复过程的更优化的起始阶段。 所公开的电路包括量化器，求和结，绝对值或平方函数和积分器。 基于固件的优化程序会导致定时控制环路经历一系列定时获取模式，每次启动不同阶段的时钟振荡器。 优化电路从每个定时获取的已知频率前导码模式中计算实际和预期采样值之间的均方误差。 最小MSE值对应于定时控制环形振荡器的更优化的起始相位。

公开(公告)号：US5886842A

公开(公告)日：1999-03-23

申请号：US920696

申请日：1997-08-29

申请人： Pablo A. Ziperovich

发明人： Pablo A. Ziperovich

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B5/596 ,  G11B20/10 ,  G11B20/14 ,  H04L7/033 ,  H04L25/06

CPC分类号： H04L25/063 ,  G11B20/10009 ,  G11B20/1426 ,  G11B5/012 ,  G11B5/09 ,  G11B5/59627 ,  H04L7/0334 ,  G11B20/1403 ,  G11B2020/1282

摘要： A power-reduced digital control within a feedback control loop of a sampling data detection channel controls a predetermined operating parameter of the channel in which an analog to digital converter provides digital samples of information in the channel at a predetermined channel clock rate. The digital control comprises a parameter error extraction circuit clocked at the predetermined channel rate which is connected to receive digital samples from the analog to digital converter, and which extracts parameter error values from the digital samples; an averaging circuit for averaging the extracted parameter error values over an integral submultiple of the predetermined channel clock rate; and a parameter error processing circuit which is connected to the parameter error extraction circuit and clocked at the integral submultiple of the predetermined channel rate for generating and putting out digital control values within the feedback control loop for controlling the predetermined operating parameter. The parameter may be timing, gain or DC offset, and the sampling data detection channel may be a PRML channel of a magnetic hard disk drive. A power-reduced control method is also described.

公开(公告)号：US5757822A

公开(公告)日：1998-05-26

申请号：US518945

申请日：1995-08-24

申请人： Kevin D. Fisher ,  Pablo A. Ziperovich

发明人： Kevin D. Fisher ,  Pablo A. Ziperovich

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B20/18 ,  H03M7/14 ,  H03M13/27 ,  H03M13/00 ,  H03M5/00 ,  H03M7/00

CPC分类号： G11B20/1866 ,  G11B20/10009 ,  G11B20/1426 ,  H03M13/27 ,  G11B2020/1434 ,  G11B2020/1446

摘要： A modulation method generates a rate 16/17 (d=0, G=7/I=11) modulation code for transferring user digital data bytes having a three-way ECC interleave through a data transfer channel in accordance with the steps of: shuffling the user data bytes in order to rearrange an order of the bytes in a predetermined manner and putting out A.sub.i B.sub.i byte pairs, encoding eight bits of the Ai bytes of the AiBi byte pairs in accordance with a predetermined rate 8/9 modulation code to produce nine code bits a0-a8, and interleaving the nine code bits a0-a8 of each Ai byte with eight unencoded bits of each Bi byte in accordance with a predetermined bitwise interleave pattern to generate the rate 16/17 modulation code. A preferred code and circuitry for the modulation method are also described.

摘要翻译： 调制方法根据以下步骤生成用于通过数据传送通道传送具有三路ECC交错的用户数字数据字节的速率16/17（d = 0，G = 7 / I = 11）调制码：洗牌 用户数据字节，以便以预定方式重新排列字节顺序并输出AiBi字节对，根据预定速率8/9调制码对AiBi字节对的Ai字节的8位进行编码，以产生9 代码比特a0-a8，并且根据预定的按位交织模式，将每个Ai字节的九个码比特a0-a8与每个Bi字节的八个未编码比特交织，以生成速率16/17调制码。 还描述了调制方法的优选代码和电路。

公开(公告)号：US5606466A

公开(公告)日：1997-02-25

申请号：US546628

申请日：1995-10-23

申请人： Kevin D. Fisher ,  Bruce Buch ,  Thomas Lau ,  Pablo A. Ziperovich

发明人： Kevin D. Fisher ,  Bruce Buch ,  Thomas Lau ,  Pablo A. Ziperovich

IPC分类号： G11B5/027 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B5/09 ,  H04N5/76

CPC分类号： G11B20/10009 ,  G11B20/1258 ,  G11B20/1426

摘要： A new method for overlapping block read events in a disk drive having synchronously sampled data detection channels is presented. In particular, the new method is for overlapping read back processing by real-time and digital signal processing of first and second data blocks from a storage medium. The method includes steps of clocking real-time and digital signal processes by a clock synchronized to the first data block while the first data block is passing by a data transducer head, clocking the digital signal processes for the first data block by an asynchronous clock operating at a nominal data clocking rate after the first data block has passed by the data transducer head and before a clock has synchronized to the second data block following the first data block, and clocking real-time signal processes for the second data block and completing clocking of the digital processes for the first data block by a clock synchronized to the second data block passing by the data transducer head. The storage medium can be a magnetic hard disk, magnetic tape, or an optical disk, for example.

摘要翻译： 提出了一种用于在具有同步采样数据检测通道的磁盘驱动器中重叠块读取事件的新方法。 特别地，新方法是通过来自存储介质的第一和第二数据块的实时和数字信号处理来重叠读回处理。 该方法包括以下步骤：通过与第一数据块同步的时钟对实时和数字信号处理进行计时，同时第一数据块通过数据传感器头，通过异步时钟操作为第一数据块的数字信号处理计时 在第一数据块经过数据变换器头之后并且在时钟已经与第一数据块之后的第二数据块同步之后的标称数据时钟速率，以及对第二数据块的实时信号处理进行计时并完成时钟 通过与数据传感器头通过的第二数据块同步的时钟来产生第一数据块的数字处理。 存储介质可以是例如磁性硬盘，磁带或光盘。

公开(公告)号：US5459679A

公开(公告)日：1995-10-17

申请号：US276817

申请日：1994-07-18

申请人： Pablo A. Ziperovich

发明人： Pablo A. Ziperovich

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  H03G3/20 ,  H03M1/10 ,  H04L25/06 ,  G06J1/00

CPC分类号： G11B20/10203 ,  G11B20/10009 ,  G11B20/10055 ,  H04L25/064 ,  G11B20/1258 ,  G11B2020/1284

摘要： An apparatus and method for removing direct current (DC) offset from a received analog signal having DC offset introduced during analog signal processing. The preferred circuit has a DC offset control loop that is enabled and operates in real-time during the reading of a sinusoidal preamble pattern. The control loop rapidly cancels DC offset by subtracting a learned correction value from the incoming analog signal being processed. Before end of preamble playback the loop is disabled and the learned correction value held during data read times. The DC offset control loop is not dependent upon correct sampling phase decisions in order to properly determine the DC offset correction value, and it is orthogonal with respect to the gain and timing control loops in a sampled data system thereby minimizing cross-talk or other interference between the several control loops.

摘要翻译： 一种用于从模拟信号处理期间引入的DC偏移的接收模拟信号中去除直流（DC）偏移的装置和方法。 优选的电路具有DC偏移控制回路，其在读取正弦前导码模式期间能够实时地操作。 控制回路通过从正在处理的输入模拟信号中减去学习校正值来快速消除DC偏移。 在前导回放结束之前，循环被禁用，并且在数据读取时间期间保持学习的校正值。 DC偏移控制环路不依赖于正确的采样相位决定，以便适当地确定DC偏移校正值，并且它与采样数据系统中的增益和定时控制环路正交，从而使串扰或其他干扰最小化 在几个控制回路之间。