公开(公告)号：US06378029B1

公开(公告)日：2002-04-23

申请号：US09295668

申请日：1999-04-21

申请人： Padmanabha I. Venkitakrishnan ,  Gopalakrishnan Janakiraman ,  Tsen-Gong Jim Hsu ,  Rajendra Kumar

发明人： Padmanabha I. Venkitakrishnan ,  Gopalakrishnan Janakiraman ,  Tsen-Gong Jim Hsu ,  Rajendra Kumar

IPC分类号： G06F1300

CPC分类号： G06F13/4243

摘要： A distributed shared memory multi-processor system includes a System Control Unit (SCU) which is made up of a system control unit address section (SCUA) and system control unit data sections (SCUDs). The SCU is scalable by dividing the control and data flow functions of the SCU, and then parallelizing the data path. This allows the number of processors in the system to be increased or higher performance processors to be added by increasing the number of SCUDs and reprogramming crossbar switches incorporated in the SCUA and SCUDs. This results in the overall increase of the multi-processor system performance.

摘要翻译： 分布式共享存储器多处理器系统包括由系统控制单元地址部分（SCUA）和系统控制单元数据部分（SCUD）组成的系统控制单元（SCU）。 通过划分SCU的控制和数据流功能，然后并行化数据路径，SCU是可扩展的。 这样就可以通过增加SCUD和SCUA中SCUD和SCU的重新编程交叉开关来增加系统中的处理器数量或增加性能处理器。 这导致多处理器系统性能的总体增长。

公开(公告)号：US06374331B1

公开(公告)日：2002-04-16

申请号：US09223469

申请日：1998-12-30

申请人： Gopalakrishnan Janakiraman ,  Tsen-Gong Jim Hsu ,  Padmanabha I. Venkitakrishnan ,  Rajendra Kumar

发明人： Gopalakrishnan Janakiraman ,  Tsen-Gong Jim Hsu ,  Padmanabha I. Venkitakrishnan ,  Rajendra Kumar

IPC分类号： G06F1200

CPC分类号： G06F12/0817 ,  G06F12/0813 ,  G06F2212/2542

摘要： A network of integrated communication switches and coherence controllers is provided which interconnected nodes in a cache-coherent multi-processor computer architecture. The nodes contain multiple processors operatively connected to associated memory units through memory controllers. The communication switches and coherence controllers has associated coherence directories which maintain coherence information for all memory lines that are “homed” in the nodes that are directly connected to the particular communication switch and coherence controller.

摘要翻译： 提供了一种集成通信交换机和一致性控制器的网络，其中高速缓存一致的多处理器计算机架构中的互连节点。 节点包含通过存储器控制器可操作地连接到相关联的存储器单元的多个处理器。 通信交换机和一致性控制器具有相关联的相干目录，其保持在直接连接到特定通信交换机和相干控制器的节点中“归属”的所有存储器线路的相干信息。

公开(公告)号：US06704842B1

公开(公告)日：2004-03-09

申请号：US09548009

申请日：2000-04-12

申请人： Gopalakrishnan Janakiraman ,  Rajendra Kumar

发明人： Gopalakrishnan Janakiraman ,  Rajendra Kumar

IPC分类号： G06F1200

CPC分类号： G06F12/0817 ,  G06F12/0862 ,  G06F2212/507

摘要： A network of memory and coherence controllers is provided which interconnected nodes in a cache-coherent multi-processor system. The nodes contain multiple processors operatively connected via respective caches to associated memory and coherence controllers. The system supports better processor utilization and better application performance by reducing the latency in accessing data by performing proactive speculative data transfers. In being proactive, the system speculates, without specific requests from the processors, as to what data transfers will reduce the latency and will make data transfers according to information derived from the system at any time that data transfers could be made.

摘要翻译： 提供了一种存储器和一致性控制器网络，其中高速缓存相干多处理器系统中的互连节点。 节点包含通过相应的高速缓存操作地连接到相关联的存储器和相干控制器的多个处理器。 该系统通过执行主动的投机数据传输，减少访问数据的延迟，从而支持更好的处理器利用率和更好的应用程序性能。 在积极主动的情况下，系统在没有来自处理器的具体请求的情况下推测什么数据传输将减少延迟，并且将根据从系统导出的信息在任何时间进行数据传输而进行数据传输。

公开(公告)号：US09071494B2

公开(公告)日：2015-06-30

申请号：US13486608

申请日：2012-06-01

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H04L27/00 ,  H04L27/26 ,  H04L27/20 ,  H03H21/00

CPC分类号： H04L27/2657 ,  H03H21/003 ,  H04L27/20 ,  H04L27/2676 ,  H04L27/2688

摘要： Systems and methods are provided for fast and precise estimation of frequency with relatively minimal sampling and relatively high tolerance to noise.

公开(公告)号：US08995542B2

公开(公告)日：2015-03-31

申请号：US13913761

申请日：2013-06-10

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H04K1/10 ,  H04L27/28 ,  H04L27/26

CPC分类号： H04L27/2602 ,  H04L27/2614 ,  H04L27/2615 ,  H04L27/2618

摘要： Various embodiments of the invention are directed to methods and systems for multi transform OFDM transmitter and receivers with low peak to average power ratio (PAPR) signals, that have high bandwidth efficiency and are computational efficient. For example, various embodiments of the transmitter may utilize an architecture comprised of a baseband modulator, a serial to parallel converter, a bank of multiplicity NT orthonormal transforms unit, a bank of multiplicity NT inverse Fourier transforms unit, a dummy symbols generator, and a minimum PAPR evaluation unit for finding the optimum transform index n0. Various embodiments of the receiver may comprise of a transform index detection unit for the detection of the transform index imbedded in the OFDM signal.

摘要翻译： 本发明的各种实施例涉及具有低峰值与平均功率比（PAPR）信号的具有高带宽效率并且具有计算效率的多变换OFDM发射机和接收机的方法和系统。 例如，发射机的各种实施例可以利用包括基带调制器，串行到并行转换器，多重组NT正交变换单元组，多重组NT逆傅里叶变换单元组，虚拟符号发生器和 用于找到最佳变换索引n0的最小PAPR评估单元。 接收机的各种实施例可以包括用于检测嵌入在OFDM信号中的变换索引的变换索引检测单元。

公开(公告)号：US08982924B2

公开(公告)日：2015-03-17

申请号：US12660615

申请日：2010-03-02

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H04B1/00 ,  G06F7/00 ,  H04L27/00 ,  H04L27/20

CPC分类号： G06F7/00 ,  H04L27/00 ,  H04L27/20

摘要： Various embodiments are directed to systems and methods for combining a plurality of codes. The plurality of codes may be binary codes having possible logical values of −1 and +1 and may comprise an even number of codes. An output of the combining v0,k may be given by: v0=sgn(vi), where vi is the sum of the first plurality of codes at the first time. Embodiments for allocating different power levels among various codes are presented.

摘要翻译： 各种实施例涉及用于组合多个代码的系统和方法。 多个代码可以是具有可能的逻辑值为-1和+1的二进制代码，并且可以包括偶数个代码。 组合v0，k的输出可以由下式给出：v0 = sgn（vi），其中vi是第一时间的第一个多个代码的和。 呈现了各种代码中分配不同功率电平的实施例。

公开(公告)号：US08711919B2

公开(公告)日：2014-04-29

申请号：US13434498

申请日：2012-03-29

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H04B1/1081 ,  H04L25/0204 ,  H04L25/0307 ,  H04L25/03292 ,  H04L27/3416 ,  H04L27/3845

摘要： Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with hierarchical structure (BMAEHS) comprised of a level 1 adaptive system and a level 2 adaptive system, and an initial data recovery subsystem. The BMAEHS may additionally be comprised of an orthogonalizer for providing a faster convergence speed. In various architectures of the invention, the BMAEHS may be replaced by a cascade of multiple equalizer stages for providing computational and other advantages. Various embodiments may employ either linear or decision feedback configurations. In the communication receiver architectures, differential encoders and decoders are presented to resolve possible ambiguities. Adaptive digital beam former architecture is presented.

摘要翻译： 本文描述的各种实施例涉及用于盲模式自适应均衡器系统的方法和系统，以从随时变分散无线信道发送的信号中恢复复值数据符号。 例如，各种实施例可以利用由信道增益归一化器，具有由1级自适应系统和2级自适应系统组成的分级结构（BMAEHS）的盲模式均衡器和初始数据恢复子系统组成的架构。 BMAEHS可以另外由用于提供更快的收敛速度的正交化器组成。 在本发明的各种架构中，BMAEHS可以由多个均衡器级联代替，以提供计算和其他优点。 各种实施例可以采用线性或决策反馈配置。 在通信接收机架构中，提出了差分编码器和解码器来解决可能的模糊性。 提出了自适应数字波束形成器架构。

公开(公告)号：US08638890B2

公开(公告)日：2014-01-28

申请号：US13465606

申请日：2012-05-07

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H03D1/04

CPC分类号： H04L27/12 ,  H04L27/156

摘要： A receiver may comprise a complex mixer for converting the modulated signal to a complex modulated signal comprising a first in-phase component and a first quadrature component. The receiver may further comprise a digital demodulator. The digital demodulator may comprise at least one processor circuit programmed for applying a phase differencer for generating an output function in terms of a phase difference of the complex modulated signal. Applying the phase differencer may comprise converting the first in-phase component to a function of a phase difference of the first in-phase component expressed in digital time, and converting the first quadrature component to a function of the phase difference of the first quadrature component expressed in digital time. The at least one processor circuit of the digital demodulator may also be programmed for applying a four quadrant inverse tangent to the output function to generate the information signal.

摘要翻译： 接收机可以包括用于将调制信号转换成包括第一同相分量和第一正交分量的复调制信号的复合混频器。 接收机还可以包括数字解调器。 数字解调器可以包括至少一个处理器电路，其被编程用于施加相位差分器，用于根据复调制信号的相位差产生输出函数。 应用相位差分器可以包括将第一同相分量转换为以数字时间表示的第一同相分量的相位差的函数，并将第一正交分量转换为第一正交分量的相位差的函数 以数字时代表达。 数字解调器的至少一个处理器电路也可以被编程为向输出功能施加四象限反正切以产生信息信号。

公开(公告)号：US08612651B2

公开(公告)日：2013-12-17

申请号：US12599062

申请日：2008-05-14

申请人： Johannes Boonstra ,  Sundaravaradan Rangarajan ,  Rajendra Kumar

发明人： Johannes Boonstra ,  Sundaravaradan Rangarajan ,  Rajendra Kumar

IPC分类号： G06F3/00 ,  G06G5/00

CPC分类号： G06F5/12

摘要： A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (10), a write pointer circuit (16) clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit (30) which has its write pointer address incremented synchronously with the write pointer circuit (16), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (10). A comparator (34) compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.

摘要翻译： FIFO存储器电路用于在具有不同时钟域的电路之间进行接口。 电路具有FIFO存储器（10），由第一时钟域的时钟定时并且控制写入数据的存储器位置的写指针电路（16）以及由第二时钟的时钟脉冲定时的读指针电路 并控制读取数据的存储器位置。 读写指针电路采用灰度编码。 存储电路还包括一个重写写指针电路（30），它具有与写指针电路（16）同步增加的写指针地址，并且具有选择的开始写地址，使得重写写指针地址落在写指针之后 地址电路由与FIFO存储器（10）的大小对应的多个地址位置。 比较器（34）将读取指针电路地址与用于确定FIFO存储器的完整状态的重复写指针电路地址进行比较。

公开(公告)号：US20130259113A1

公开(公告)日：2013-10-03

申请号：US13434498

申请日：2012-03-29

申请人： Rajendra Kumar

发明人： Rajendra Kumar

IPC分类号： H04L27/01 ,  H04B1/16

CPC分类号： H04L25/03885 ,  H04B1/1081 ,  H04L25/0204 ,  H04L25/0307 ,  H04L25/03292 ,  H04L27/3416 ,  H04L27/3845

摘要： Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive wireless channels. For example, various embodiments may utilize an architecture comprised of a channel gain normalizer, a blind mode equalizer with hierarchical structure (BMAEHS) comprised of a level 1 adaptive system and a level 2 adaptive system, and an initial data recovery subsystem. The BMAEHS may additionally be comprised of an orthogonalizer for providing a faster convergence speed. In various architectures of the invention, the BMAEHS may be replaced by a cascade of multiple equalizer stages for providing computational and other advantages. Various embodiments may employ either linear or decision feedback configurations. In the communication receiver architectures, differential encoders and decoders are presented to resolve possible ambiguities. Adaptive digital beam former architecture is presented.

摘要翻译： 本文描述的各种实施例涉及用于盲模式自适应均衡器系统的方法和系统，以从随时变分散无线信道发送的信号中恢复复值数据符号。 例如，各种实施例可以利用由信道增益归一化器，具有由1级自适应系统和2级自适应系统组成的分级结构（BMAEHS）的盲模式均衡器和初始数据恢复子系统组成的架构。 BMAEHS可以另外由用于提供更快的收敛速度的正交化器组成。 在本发明的各种架构中，BMAEHS可以由多个均衡器级联代替，以提供计算和其他优点。 各种实施例可以采用线性或决策反馈配置。 在通信接收机架构中，提出了差分编码器和解码器来解决可能的模糊性。 提出了自适应数字波束形成器架构。