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公开(公告)号：US20090316509A1
公开(公告)日：2009-12-24
申请号：US12144332
申请日：2008-06-23
摘要： A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier.
摘要翻译： 包括数据线，读出放大器和存储器单元阵列的存储器。 存储器包括用于将数据线耦合到用于读取的阵列的存储器单元的晶体管。 晶体管被偏置在高于在预充电期间数据线偏置的电压的电压。 晶体管是调节电路的一部分。 调节电路包括具有比读出放大器的晶体管更高的介电击穿电压的晶体管。
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公开(公告)号：US07701785B2
公开(公告)日：2010-04-20
申请号：US12144332
申请日：2008-06-23
IPC分类号： G11C7/00
摘要： A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier.
摘要翻译： 包括数据线，读出放大器和存储器单元阵列的存储器。 存储器包括用于将数据线耦合到用于读取的阵列的存储器单元的晶体管。 晶体管被偏置在高于在预充电期间数据线偏置的电压的电压。 晶体管是调节电路的一部分。 调节电路包括具有比读出放大器的晶体管更高的介电击穿电压的晶体管。
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3.发明授权Memory device and method using encode values for access error condition detection 有权存储器件和使用编码值进行访问错误状态检测的方法公开(公告)号：US08625365B2
公开(公告)日：2014-01-07
申请号：US13212478
申请日：2011-08-18
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C7/1006
摘要： A memory module decodes an address to determine a one or more wordline select pattern, or other spatial select pattern. An encoder determines an encoded value based upon the wordline select pattern that is compared to an expected encode value. The encode value has fewer than twice the number of address bits used to determine the wordline select pattern.
摘要翻译： 存储器模块解码地址以确定一个或多个字线选择模式或其他空间选择模式。 编码器基于与预期编码值进行比较的字线选择模式来确定编码值。 编码值的位数少于用于确定字线选择模式的地址位数的两倍。
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4.发明授权Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage 有权带有字线驱动器/解码器的非易失性存储器（NVM）使用电荷泵电压公开(公告)号：US08913436B2
公开(公告)日：2014-12-16
申请号：US13826958
申请日：2013-03-14
摘要： A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.
摘要翻译： 一种字线驱动器，其包括用于偏置位于高电源电压端子和低电源电压端子之间的晶体管堆叠的节点的上拉晶体管。 节点偏置在高电源电压和低电源电压之间的电压。 晶体管堆叠包括一堆解码晶体管和共源共栅晶体管。 共源共栅晶体管位于节点和耦合到反相电路的堆叠的第二节点之间。
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公开(公告)号：US07692989B2
公开(公告)日：2010-04-06
申请号：US11740331
申请日：2007-04-26
IPC分类号： G11C7/00
CPC分类号： G11C16/28 , G11C16/3436
摘要： A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a program/erase controller. The verify data line has a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output. A second logic circuit has a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output. A global data line is coupled to a second output of the first sense amplifier and a second output of the second sense amplifier. A global sense amplifier is coupled to the global data line.
摘要翻译： 存储器具有分别耦合到第一和第二存储器阵列的第一和第二存储器阵列以及第一和第二读出放大器。 验证数据线耦合到第一读出放大器和第二读出放大器的第一输出以及编程/擦除控制器。 验证数据线具有第一逻辑电路，其具有耦合到第一读出放大器的第一输出的第一输入和输出。 第二逻辑电路具有耦合到第一逻辑电路的输出的第一输入，耦合到第二读出放大器的第一输出的第二输入和输出。 全局数据线耦合到第一读出放大器的第二输出端和第二读出放大器的第二输出端。 全局读出放大器耦合到全局数据线。
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公开(公告)号：US20130044558A1
公开(公告)日：2013-02-21
申请号：US13212478
申请日：2011-08-18
IPC分类号： G11C8/10
CPC分类号： G11C8/12 , G11C7/1006
摘要： A memory module decodes an address to determine a one or more wordline select pattern, or other spatial select pattern. An encoder determines an encoded value based upon the wordline select pattern that is compared to an expected encode value. The encode value has fewer than twice the number of address bits used to determine the wordline select pattern.
摘要翻译： 存储器模块解码地址以确定一个或多个字线选择模式或其他空间选择模式。 编码器基于与预期编码值进行比较的字线选择模式来确定编码值。 编码值的位数少于用于确定字线选择模式的地址位数的两倍。
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公开(公告)号：US07733126B1
公开(公告)日：2010-06-08
申请号：US12415159
申请日：2009-03-31
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , G11C16/14 , G11C16/30 , H03K3/356113
摘要： A first logic state is at a first output voltage level at a first output of a level shifter that selects a first negative regulation voltage level in response to the first logic state. A negative supply voltage begins at first potential and decreases to the first negative regulation voltage level. The first output voltage level decreases as the negative supply voltage decreases. The first output of the level shifter is switched from the first logic state to a second logic state in response to the negative supply voltage reaching the first negative regulation voltage level. The second logic state is provided at a second output voltage level that selects a second negative regulation voltage level for the negative regulation voltage. The first output of the level shifter remains at the second logic state but is reduced in voltage.
摘要翻译： 电平移位器的第一输出处的第一逻辑状态处于第一输出电压电平，其响应于第一逻辑状态选择第一负调节电压电平。 负电源电压从第一个电位开始并降低到第一个负调节电压电平。 第一个输出电压电平随负电源电压降低而减小。 响应于负电源电压达到第一负调节电压电平，电平移位器的第一输出从第一逻辑状态切换到第二逻辑状态。 第二逻辑状态被提供在第二输出电压电平，其选择用于负调节电压的第二负调节电压电平。 电平移位器的第一个输出保持在第二个逻辑状态，但电压降低。
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公开(公告)号：US20080266974A1
公开(公告)日：2008-10-30
申请号：US11740331
申请日：2007-04-26
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C16/3436
摘要： A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a program/erase controller. The verify data line has a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output. A second logic circuit has a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output. A global data line is coupled to a second output of the first sense amplifier and a second output of the second sense amplifier. A global sense amplifier is coupled to the global data line.
摘要翻译： 存储器具有分别耦合到第一和第二存储器阵列的第一和第二存储器阵列以及第一和第二读出放大器。 验证数据线耦合到第一读出放大器和第二读出放大器的第一输出以及编程/擦除控制器。 验证数据线具有第一逻辑电路，其具有耦合到第一读出放大器的第一输出的第一输入和输出。 第二逻辑电路具有耦合到第一逻辑电路的输出的第一输入，耦合到第二读出放大器的第一输出的第二输入和输出。 全局数据线耦合到第一读出放大器的第二输出端和第二读出放大器的第二输出端。 全局读出放大器耦合到全局数据线。
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公开(公告)号：US08737137B1
公开(公告)日：2014-05-27
申请号：US13747088
申请日：2013-01-22
申请人： Jon S. Choy , Padmaraj Sanjeevarao
发明人： Jon S. Choy , Padmaraj Sanjeevarao
IPC分类号： G11C16/06
摘要： A memory device includes a word line driver circuit, a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit, and a write bias generator including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit. The write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit.
摘要翻译： 存储器件包括字线驱动器电路，写入电压发生器，用于在对与字线驱动器电路耦合的存储器单元的写入操作期间向字线驱动器提供写入电压;以及写入偏置发生器，其包括用于提供 在对与字线驱动电路耦合的存储单元的写入操作期间，写入偏置电压与写入电压不同于字线驱动器电路。 写入偏置电压用于在写入操作期间将由字线驱动器电路从写入电压发生器引起的电流减小到耦合到字线驱动器电路的存储器单元。
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公开(公告)号：US07055118B1
公开(公告)日：2006-05-30
申请号：US10790650
申请日：2004-03-01
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and apparatus for improved formal scan chain equivalence checking to verify the operation of components in a VLSI integrated circuit is described in connection with using symbolic simulation for verification of scan chain equivalency between different modeling representations of a circuit-under-test. The present invention enhances previous techniques by loading each scannable state-element in the circuit design with a symbolic expression that characterizes the logical location of the element and performing a scan shift operation to verify the contents of each scannable state-element at the scan-out and other primary output pins of the design.
摘要翻译： 结合使用符号仿真来验证被测电路的不同建模表示之间的扫描链等效性，描述了用于改进的形式扫描链等效性检查以验证VLSI集成电路中的组件的操作的方法和装置。 本发明通过在电路设计中加载表征元件的逻辑位置的符号表达来执行扫描移位操作来验证扫描出的每个可扫描状态元件的内容来增强先前的技术， 和其他主要输出引脚的设计。
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