公开(公告)号：US10324664B2

公开(公告)日：2019-06-18

申请号：US15079901

申请日：2016-03-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hirokazu So ,  Toshiyuki Honda ,  Shigekazu Kogita

IPC: G06F3/06 ,  G06F12/02

Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.

公开(公告)号：US09965202B2

公开(公告)日：2018-05-08

申请号：US15079959

申请日：2016-03-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shigekazu Kogita ,  Hirokazu So ,  Toshiyuki Honda

IPC: G06F3/06 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3431

Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.

公开(公告)号：US09778857B2

公开(公告)日：2017-10-03

申请号：US14611784

申请日：2015-02-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takuji Maeda ,  Masayuki Toyama ,  Hirokazu So

IPC: G06F12/00 ,  G06F3/06 ,  H04N5/907 ,  H04N5/91

CPC classification number: G06F3/0613 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  H04N5/907 ,  H04N5/91

Abstract: A recording device operates in accordance with an instruction from an access device. The recording device comprising a nonvolatile memory that stores data, a communication unit that receives an instruction issued by the access device, and a memory controller that controls the nonvolatile memory. When a recording instruction for recording data into the nonvolatile memory is received from the access device, the memory controller starts recording of data into the nonvolatile memory. When the memory controller receives from the access device a suspension instruction for suspending the recording of data, the memory controller stores suspension information into the nonvolatile memory, the suspension information indicating a suspended position as a position in a recording area of the nonvolatile memory at which the data is being recorded upon reception of the suspension instruction.