公开(公告)号：US20220308893A1

公开(公告)日：2022-09-29

申请号：US17841054

申请日：2022-06-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi ONO ,  Isao KATO ,  Takuji MAEDA

IPC: G06F9/4401 ,  G06F1/06 ,  G06F1/3215

Abstract: A slave device continuously transmits a plurality of tuning blocks to a host device at intervals defined by a clock period between a plurality of data blocks at the time of transmitting the plurality of data blocks and by a clock period defined by a data structure of the plurality of tuning blocks.

公开(公告)号：US20200034317A1

公开(公告)日：2020-01-30

申请号：US16592967

申请日：2019-10-04

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Isao KATO ,  Osamu SHIBATA

IPC: G06F13/16 ,  G06F13/42 ,  G06F1/26

Abstract: A slave device is to be connected to a host device through at least one of a first interface and a second interface. The slave device includes a first terminal group used for the first interface, a second terminal group used for the second interface and a signal input and output part. The first terminal group and the second terminal group are provided at positions identical to terminal groups of another slave device to be connected through a third interface different from the second interface. The signal input and output part supplies a signal to a predetermined terminal in the first terminal group within a predetermined period from supply of power to the slave device, the signal notifying the host device whether the second terminal group is compliant with the second interface.

公开(公告)号：US20250004448A1

公开(公告)日：2025-01-02

申请号：US18883383

申请日：2024-09-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshihisa INAGAKI ,  Tadashi ONO ,  Isao KATO

IPC: G05B19/4155

Abstract: A memory card is configured to be inserted into and removed from a connector provided in a host device, and includes: a memory that stores heat dissipator information on a heat dissipator of the memory card; and a processor that returns a response including the heat dissipator information in response to a command for inquiring heat dissipation performance transmitted from the host device.

公开(公告)号：US20220413709A1

公开(公告)日：2022-12-29

申请号：US17897714

申请日：2022-08-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Isao KATO ,  Takuji MAEDA ,  Tadashi ONO

IPC: G06F3/06

Abstract: A storage system includes a nonvolatile memory, a controller that controls writing and reading of data to and from the nonvolatile memory, a first interface, and a second interface, and is connected to a host device via the first interface and the second interface. While the host device is being started, a boot loader read from the nonvolatile memory is transferred to the host device via the second interface, and the first interface is initialized in parallel. After the host device is started, write data and read data to or from the nonvolatile memory via any one or both of the first interface and the second interface.

公开(公告)号：US20220253092A1

公开(公告)日：2022-08-11

申请号：US17729520

申请日：2022-04-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi ONO ,  Isao KATO

IPC: G06F1/10 ,  G06F1/08 ,  G06F9/4401

Abstract: A data transfer system includes a slave device, and a host device that is connected to the slave device via at least a power supply line, a clock line, a command line, and a data line. A CMD line is continuously driven to a low level in a period from when the supply of at least a first clock is stopped to when the second clock is supplied (period form timing t5 to timing t6).

公开(公告)号：US20210209038A1

公开(公告)日：2021-07-08

申请号：US17208354

申请日：2021-03-22

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tadashi ONO ,  Isao KATO ,  Yoshihisa INAGAKI ,  Shuichi OHKI

IPC: G06F13/16 ,  G06F13/42

Abstract: When a part of a signal line of a first interface and a part of a signal line of a second interface share a signal line and there is a memory connected to both the interfaces, initialization of the second interface and initialization of the memory are executed in parallel following initialization of the first interface.