公开(公告)号：US20170177239A1

公开(公告)日：2017-06-22

申请号：US15451884

申请日：2017-03-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi ONO

IPC: G06F3/06 ,  G06F12/122 ,  G06F12/128

CPC classification number: G06F12/1027 ,  G06F3/0607 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/128 ,  G06F2212/68 ,  G06F2212/70 ,  G06F2212/7203

Abstract: Provided is a memory device with improved memory region usage efficiency. The memory device includes flash memory including: a control information (FAT) region that stores FAT for a file and a user data (UD) region that stores UD; cache memory including a FAT cache region that stores all or part of the FAT; an I/F that receives a write command for writing one of the FAT and the UD; and a memory controller that determines whether write data to be written is the FAT or the UD based on an address included in the write command, and sets the size of the FAT cache region based on an update frequency or an update count for the address included in the write command for the write data determined to be the FAT by the determiner.

公开(公告)号：US20220308893A1

公开(公告)日：2022-09-29

申请号：US17841054

申请日：2022-06-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi ONO ,  Isao KATO ,  Takuji MAEDA

IPC: G06F9/4401 ,  G06F1/06 ,  G06F1/3215

Abstract: A slave device continuously transmits a plurality of tuning blocks to a host device at intervals defined by a clock period between a plurality of data blocks at the time of transmitting the plurality of data blocks and by a clock period defined by a data structure of the plurality of tuning blocks.

公开(公告)号：US20170192919A1

公开(公告)日：2017-07-06

申请号：US15397999

申请日：2017-01-04

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi ONO ,  Tatsuya ADACHI

IPC: G06F13/364 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: In a removable system formed from a host device and a slave device detachable from the host device, when the slave device sequentially detects a signal of a first voltage level and a signal of a second voltage level from the connected host device, the signal of the first voltage level is transmitted by a second signal line. Subsequently, when the host device detects that the second signal line is at the first voltage level, the host device interrupts drive of a first signal line, and executes initialization.

公开(公告)号：US20220253092A1

公开(公告)日：2022-08-11

申请号：US17729520

申请日：2022-04-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi ONO ,  Isao KATO

IPC: G06F1/10 ,  G06F1/08 ,  G06F9/4401

Abstract: A data transfer system includes a slave device, and a host device that is connected to the slave device via at least a power supply line, a clock line, a command line, and a data line. A CMD line is continuously driven to a low level in a period from when the supply of at least a first clock is stopped to when the second clock is supplied (period form timing t5 to timing t6).

公开(公告)号：US20210209038A1

公开(公告)日：2021-07-08

申请号：US17208354

申请日：2021-03-22

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tadashi ONO ,  Isao KATO ,  Yoshihisa INAGAKI ,  Shuichi OHKI

IPC: G06F13/16 ,  G06F13/42

Abstract: When a part of a signal line of a first interface and a part of a signal line of a second interface share a signal line and there is a memory connected to both the interfaces, initialization of the second interface and initialization of the memory are executed in parallel following initialization of the first interface.

公开(公告)号：US20200034321A1

公开(公告)日：2020-01-30

申请号：US16592663

申请日：2019-10-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi ONO

IPC: G06F13/362 ,  G06F13/38 ,  G06F13/42 ,  G06F9/4401 ,  G06F9/30

Abstract: A host device is connected to either a first slave device supporting a first interface or a second slave device supporting a second interface that is different from the first interface. The host device includes an I/F controller that initializes the first interface to a first device connected to the host device, and determines whether or not the first device is the second slave device when the first interface is successfully initialized, and a host-device I/F unit that initializes the second interface if the first device is the second slave device, and continues the initialization of the first interface if the first device is not the second slave device.

公开(公告)号：US20220413709A1

公开(公告)日：2022-12-29

申请号：US17897714

申请日：2022-08-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Isao KATO ,  Takuji MAEDA ,  Tadashi ONO

IPC: G06F3/06

Abstract: A storage system includes a nonvolatile memory, a controller that controls writing and reading of data to and from the nonvolatile memory, a first interface, and a second interface, and is connected to a host device via the first interface and the second interface. While the host device is being started, a boot loader read from the nonvolatile memory is transferred to the host device via the second interface, and the first interface is initialized in parallel. After the host device is started, write data and read data to or from the nonvolatile memory via any one or both of the first interface and the second interface.

公开(公告)号：US20250004448A1

公开(公告)日：2025-01-02

申请号：US18883383

申请日：2024-09-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshihisa INAGAKI ,  Tadashi ONO ,  Isao KATO

IPC: G05B19/4155

Abstract: A memory card is configured to be inserted into and removed from a connector provided in a host device, and includes: a memory that stores heat dissipator information on a heat dissipator of the memory card; and a processor that returns a response including the heat dissipator information in response to a command for inquiring heat dissipation performance transmitted from the host device.

公开(公告)号：US20230221791A1

公开(公告)日：2023-07-13

申请号：US18122977

申请日：2023-03-17

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Tadashi ONO ,  Yoshihisa INAGAKI

IPC: G06F1/3296 ,  G06F1/04

CPC classification number: G06F1/3296 ,  G06F1/04

Abstract: When a host-slave system including a host device and a slave device transitions to a power-down mode, the host device drives a CMD line in order of a high level, a low level, and a high level, and stops supplying a clock signal after a predetermined time elapses. During a power-down mode period, the slave device stops supplying a power to a back-end module. When the host device resumes the supply of the clock signal, the host-slave system returns from the power-down mode.