公开(公告)号：US20180352179A1

公开(公告)日：2018-12-06

申请号：US15986478

申请日：2018-05-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MAKOTO SHOUHO ,  MASAAKI YANAGIDA

IPC: H04N5/357 ,  H01L27/30 ,  H04N5/378 ,  H04N5/363

CPC classification number: H04N5/3575 ,  H04N5/35509 ,  H04N5/3598 ,  H04N5/378

Abstract: An imaging device includes: a pixel; a signal line electrically connected to the pixel; and a first and second sample-and-hold circuits electrically connected to the signal line. The pixel includes: a photoelectric converter that generates signal charge; a charge accumulation region that accumulates the signal charge; a reset transistor that resets a voltage of the charge accumulation region; and an amplifier transistor that amplifies a signal voltage. The first sample-and-hold circuit includes: a first switch that is electrically connected to the signal line and has input-output characteristics in which an output is clipped at a clipping voltage with respect to an input exceeding the clipping voltage; and a first capacitor electrically connected to the signal line through the first switch. The second sample-and-hold circuit includes: a second switch electrically connected to the signal line; and a second capacitor electrically connected to the signal line through the second switch.

公开(公告)号：US20230292017A1

公开(公告)日：2023-09-14

申请号：US18317356

申请日：2023-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MAKOTO SHOUHO ,  SHINICHI MACHIDA

IPC: H04N25/532 ,  H04N25/77 ,  H04N25/709

CPC classification number: H04N25/532 ,  H04N25/77 ,  H04N25/709

Abstract: An imaging device includes a photoelectric conversion layer, a counter electrode, a first electrode, a second electrode, a first transfer gate, a second transfer gate, a first amplification transistor, and a second amplification transistor. The first transistor outputs a signal corresponding to the potential of the first gate in a first readout period in which the first transfer gate suppresses transfer of signal charges. The first readout period includes a first period in which the second transfer gate allows transfer of signal charges. The second transistor outputs a signal corresponding to the potential of the second gate in a second readout period in which the second transfer gate suppresses transfer of signal charges. The second readout period includes a second period in which the first transfer gate allows transfer of signal charges.

公开(公告)号：US20230336886A1

公开(公告)日：2023-10-19

申请号：US18340886

申请日：2023-06-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASASHI MURAKAMI ,  MAKOTO SHOUHO ,  YOSHIHIRO SATO ,  KAZUKO NISHIMURA ,  JUNJI HIRASE

IPC: H04N25/59 ,  H01L27/146

CPC classification number: H04N25/59 ,  H01L27/14643 ,  H01L27/14612

Abstract: An imaging device includes a charge accumulator, a first transistor, and a first capacitive element. The first transistor has a first source, a first drain, and a first gate electrode electrically connected to one of the first source and the first drain. The first capacitive element holds the charges and has a first terminal. A fixed potential is supplied to the other of the first source and the first drain. One of the first source and the first drain is always electrically connected to the first terminal of the first capacitive element from start to end of an exposure period.

公开(公告)号：US20240259708A1

公开(公告)日：2024-08-01

申请号：US18634097

申请日：2024-04-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MAKOTO SHOUHO

IPC: H04N25/709 ,  H04N25/53 ,  H04N25/65

CPC classification number: H04N25/709 ,  H04N25/53 ,  H04N25/65

Abstract: An imaging device includes unit pixel cells arranged in rows and columns and a voltage supply circuit. Each of the unit pixel cells includes a pixel electrode, a counter electrode, a photoelectric conversion layer converting light into signal charge, and a charge accumulation region electrically connected to the pixel electrode to accumulate signal charge. The unit pixel cells form pixel blocks each including one or more rows. The counter electrode is continuous between pixels in each pixel block and is separated between different pixel blocks. The voltage supply circuit sequentially performs a shutter operation on the pixel blocks at different timings. The shutter operation forms an exposure period by applying a first voltage to the counter electrode and forms a non-exposure period by applying a second voltage to the counter electrode.

公开(公告)号：US20240089621A1

公开(公告)日：2024-03-14

申请号：US18508277

申请日：2023-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： YASUO MIYAKE ,  MAKOTO SHOUHO

IPC: H04N25/59 ,  H04N25/771

CPC classification number: H04N25/59 ,  H04N25/771 ,  H04N25/65

Abstract: An imaging device includes a first pixel, a second pixel, and a correction circuit. First signals respectively corresponding to the first pixel and the second pixel are input to the correction circuit. The correction circuit outputs second signals in response to the first signals. Each of the first pixel and the second pixel includes a photoelectric converter, a charge storage region, and a capacitance circuit. The photoelectric converter converts light into signal charges. The charge storage region stores the signal charges. The capacitance circuit varies a capacitance value of the charge storage region in response to a potential of the charge storage region. The correction circuit corrects the first signal of at least one of the first pixel or the second pixel to the second signal in a case where the same amount of light is incident on the first pixel and the second pixel.