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公开(公告)号：US20230274864A1
公开(公告)日：2023-08-31
申请号：US18173598
申请日：2023-02-23
Inventor： Yuto AKIYAMA , Ken YANAI , Masashi TAKAMURA , Yuji YAMAGISHI , Ryosuke USUI
Abstract: A multilayer varistor according to the present disclosure includes: a sintered compact having, on a surface thereof, at least one planar portion and at least one corner portion; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the at least one planar portion and the at least one corner portion of the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes: a first high-resistivity layer covering the at least one planar portion; and a second high-resistivity layer covering the at least one corner portion. The first high-resistivity layer has a larger average thickness than the second high-resistivity layer.
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Patent Agency Ranking
公开(公告)号：US20240105365A1
公开(公告)日：2024-03-28
申请号：US18264034
申请日：2022-02-18
Inventor： Yuto AKIYAMA , Masashi TAKAMURA , Ken YANAI
Abstract: An object of the present disclosure is to provide a multilayer varistor with the ability to reduce the chances of causing crosstalk between external terminals. Inside a sintered body having the shape of a rectangular parallelepiped, of which the longitudinal axis is aligned with a first direction, a first facing portion and a second facing portion are provided to interpose a third facing portion between themselves. At least one of a first side surface or a second side surface is provided with a first external electrode connected to the first facing portion, a second external electrode connected to the second facing portion, and a third external electrode and a fourth external electrode connected to the third facing portion. In the first direction, the first external electrode and the second external electrode are interposed between the third external electrode and the fourth external electrode.
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公开(公告)号：US20230326636A1
公开(公告)日：2023-10-12
申请号：US18182134
申请日：2023-03-10
Inventor： Masashi TAKAMURA , Yuto AKIYAMA , Ken YANAI
CPC classification number: H01C7/1006 , H01C1/14 , H01C7/102 , H01C7/112
Abstract: A multilayer varistor includes a sintered body and a first internal electrode, a second internal electrode, a third internal electrode, and a fourth internal electrode which are disposed in the sintered body. The first internal electrode, the second internal electrode, the third internal electrode, and the fourth internal electrode are arranged in an order of the first internal electrode, the third internal electrode, the fourth internal electrode, and the second internal electrode from a side of a first main face. The third internal electrode and the fourth internal electrode are electrically connected to each other. At least part of the first internal electrode and at least part of the third internal electrode overlap each other when viewed in a third direction. At least part of the second internal electrode and at least part of the fourth internal electrode overlap each other when viewed in the third direction.
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公开(公告)号：US20230274863A1
公开(公告)日：2023-08-31
申请号：US18173584
申请日：2023-02-23
Inventor： Yuto AKIYAMA , Ken YANAI , Ryosuke USUI , Yuji YAMAGISHI , Masashi TAKAMURA
Abstract: A multilayer varistor according to the present disclosure includes; a sintered compact; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes a thinner region having a smaller thickness than a surrounding region that surrounds the thinner region.
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公开(公告)号：US20250087393A1
公开(公告)日：2025-03-13
申请号：US18957218
申请日：2024-11-22
Inventor： Masashi TAKAMURA , Ken YANAI , Sayaka WATANABE , Tomomitsu MURAISHI
Abstract: A stacked varistor having a small variation in electrostatic capacitance is obtained. The stacked varistor includes first internal electrode projection extending from third internal electrode toward first end surface between first side surface and first varistor region, and second internal electrode projection extending from third internal electrode toward second end surface between first side surface and second varistor region. First internal electrode projection extends closer to first end surface than a line connecting point closest to first end surface of first varistor region and point closest to first end surface of third external electrode is. Second internal electrode projection extends closer to second end surface than a line connecting point closest to second end surface of second varistor region and point closest to second end surface of third external electrode is.
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公开(公告)号：US20230079197A1
公开(公告)日：2023-03-16
申请号：US17796143
申请日：2021-12-17
Inventor： Masashi TAKAMURA , Sayaka WATANABE , Takeshi FUJII , Ken YANAI , Yuto AKIYAMA
Abstract: A multilayer varistor has a stack structure including a plurality of layers stacked in a third direction. The multilayer varistor includes a first internal electrode electrically connected to a first external electrode, a second internal electrode electrically connected to the second external electrode, and a third internal electrode electrically connected to the third external electrode. The first internal electrode is disposed between the second internal electrode and the third internal electrode in the third direction.
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