公开(公告)号：US09921975B2

公开(公告)日：2018-03-20

申请号：US14685038

申请日：2015-04-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshikazu Katoh ,  Takuji Maeda ,  Shinji Inoue ,  Masato Suto

IPC: G06F12/14 ,  G09C1/00 ,  G11C13/00 ,  G11C7/10 ,  G06F21/31 ,  G06F21/73 ,  G06F21/79

CPC classification number: G06F12/1408 ,  G06F21/31 ,  G06F21/73 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/2107 ,  G09C1/00 ,  G11C7/1006 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  H04L2209/12

Abstract: A cryptographic processing device comprises a cipher control circuit operative to execute at least one of encryption of plaintext data and decryption of ciphertext data on the basis of conversion parameter data; and a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including the conversion parameter data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.

公开(公告)号：US09804921B2

公开(公告)日：2017-10-31

申请号：US14968830

申请日：2015-12-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masato Suto

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/05

CPC classification number: G06F11/1048 ,  H03M13/05

Abstract: A nonvolatile memory apparatus is provided with a nonvolatile memory including a plurality of blocks each being a recording area of the data and a unit of erasing of the data, and a controller for controlling writing or reading of the data to/from the nonvolatile memory. Each of the blocks includes pages each being a unit of reading of the data. The controller, when data of a first page is read in response to the data read request from the external apparatus, reads data of an other page other than the first page in a block from which the data is read, and calculates a number of errors of the data in the other page, and rewrites the data into an other block when the block from which the data is read satisfies a predetermined condition on the error based on the calculated number of errors.