公开(公告)号：US10983929B2

公开(公告)日：2021-04-20

申请号：US16584487

申请日：2019-09-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shinji Inoue

IPC: G06F13/16 ,  G06F13/42

Abstract: In an information processing device serving as a PCIe system including a host device and a plurality of memory devices, one of the plurality of memory devices is defined as a master memory. The other memory devices are defined as slave memories, and are logically coupled to the master memory. The plurality of memory devices thus constitute a single virtual storage. When accessing is performed from a root complex to the plurality of memory devices constituting the single virtual storage, the root complex hands over a bus master to the master memory. The master memory receives a command regarding the accessing from the root complex, changes address information used for the accessing in the command regarding the accessing, based on a logical relationship with the slave memories, and sends changed command regarding the accessing to the slave memories.

公开(公告)号：US09921975B2

公开(公告)日：2018-03-20

申请号：US14685038

申请日：2015-04-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshikazu Katoh ,  Takuji Maeda ,  Shinji Inoue ,  Masato Suto

IPC: G06F12/14 ,  G09C1/00 ,  G11C13/00 ,  G11C7/10 ,  G06F21/31 ,  G06F21/73 ,  G06F21/79

CPC classification number: G06F12/1408 ,  G06F21/31 ,  G06F21/73 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/2107 ,  G09C1/00 ,  G11C7/1006 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  H04L2209/12

Abstract: A cryptographic processing device comprises a cipher control circuit operative to execute at least one of encryption of plaintext data and decryption of ciphertext data on the basis of conversion parameter data; and a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including the conversion parameter data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.

公开(公告)号：US11977501B2

公开(公告)日：2024-05-07

申请号：US17572904

申请日：2022-01-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shinji Inoue

IPC: G06F13/16 ,  B60R16/023 ,  B60R22/48 ,  B60R25/24 ,  B60R25/31 ,  B60R25/34 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F13/1684 ,  B60R16/0231 ,  B60R22/48 ,  B60R25/245 ,  B60R25/31 ,  B60R25/34 ,  G06F3/0604 ,  G06F3/0632 ,  G06F12/0246 ,  B60R2022/4808 ,  G06F2212/72 ,  G07C2209/63

Abstract: The present disclosure provides an on-board storage system in which the time required for initializing a storage device is substantially shortened by devising a backend start timing. The on-board storage system includes: a storage device that has a controller, a NAND flash memory, and an interface; an electronic control unit that electronically controls a vehicle; and a sensor. The electronic control unit communicates with the storage device through the interface, the sensor transmits a detection result of the sensor to the electronic control unit, and the electronic control unit transmits a command to start initialization of the NAND flash memory to the controller when the transmitted detection result of the sensor indicates a driving-start preliminary operation.

公开(公告)号：US09811476B2

公开(公告)日：2017-11-07

申请号：US14769615

申请日：2014-02-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takuji Maeda ,  Shinji Inoue ,  Yoshikazu Katoh

IPC: H04L9/32 ,  G06F12/14 ,  G06F21/62 ,  H04L9/14 ,  H04L9/08 ,  G06F12/02

CPC classification number: G06F12/1408 ,  G06F12/0238 ,  G06F21/62 ,  G06F2212/1052 ,  G06F2212/202 ,  H04L9/088 ,  H04L9/0897 ,  H04L9/14 ,  H04L2209/605

Abstract: An encryption and recording apparatus storing data, the apparatus including: a first nonvolatile memory; a second nonvolatile memory; and an encryption and decryption control unit, wherein the encryption and decryption control unit: manages an area included in the second nonvolatile memory on a per-block basis, and manages association between a block and a block-unique key using key management information stored in the first nonvolatile memory; receives the data and corresponding information associated with the data; encrypts the data, using one or more block-unique keys associated with one or more blocks included in the second nonvolatile memory and writes the data to the one or more blocks; and stores the corresponding information into the key management information, associating the corresponding information and the one or more block-unique keys.

公开(公告)号：US11983304B2

公开(公告)日：2024-05-14

申请号：US17573827

申请日：2022-01-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shinji Inoue

IPC: G06F21/78 ,  G06F3/06 ,  G06F21/31

CPC classification number: G06F21/78 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0673 ,  G06F21/31

Abstract: The present disclosure provides an on-board secure storage system capable of easily and quickly detecting unauthorized access to a storage device and a failure of the storage device, and appropriately using the detection result. the on-board secure storage system includes the storage device that has a controller, a non-volatile memory and an interface, and an electronic control unit that electronically controls a vehicle. After determining that unauthorized access or a failure occurs in the non-volatile memory, the controller performs predetermined processing according to the type of the unauthorized access or failure.