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公开(公告)号：US10096359B2
公开(公告)日：2018-10-09
申请号：US15594927
申请日：2017-05-15
Inventor： Yuhei Yoshimoto , Yoshikazu Katoh
Abstract: A nonvolatile memory device includes: resistive memory cells each of which takes either a variable state or an initial state, the resistive memory cells including at least one resistive memory cell in the initial state; and a read circuit that includes a resistance detection circuit that obtains resistance value information of the at least one resistive memory cell, and a data generation circuit that generates digital data corresponding to the resistance value information. The resistance detection circuit applies a second read voltage to the at least one resistive memory cell to obtain the resistance value information. The second read voltage is larger than a first read voltage and smaller than a voltage of a forming pulse that is an electrical stress for changing from the initial state to the variable state. The first read voltage is for reading a resistive memory cell in the variable state.
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公开(公告)号：US10049734B2
公开(公告)日：2018-08-14
申请号：US14677708
申请日：2015-04-02
Inventor： Yoshikazu Katoh
Abstract: A data storing method comprises preparing a non-volatile memory device that includes a memory cell array including a plurality of memory cells, wherein the plurality of memory cells include a memory cell in an initial state, which does not change, unless a forming stress is applied thereto, to a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and applying the forming stress to the memory cell in the initial state, to store data in the memory cell array on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.
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公开(公告)号：US09600237B2
公开(公告)日：2017-03-21
申请号：US14679722
申请日：2015-04-06
Inventor： Yoshikazu Katoh
CPC classification number: G06F7/58 , G06F5/01 , G06F7/588 , G11C13/0002 , G11C13/0007
Abstract: A random number processing apparatus includes a memory cell and a control circuitry. The memory cell has a characteristic in which a resistance value reversibly shifts between a plurality of resistance value ranges in accordance with an electric signal applied. The control circuitry generates random number data on the basis of a plurality of items of resistance value information obtained, at a plurality of different times, from the memory cell whose resistance value is in a certain resistance value range of the plurality of resistance value ranges. The resistance value of the memory cell randomly changes over time while the resistance value is within the certain resistance value range.
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公开(公告)号：US09948471B2
公开(公告)日：2018-04-17
申请号：US15181430
申请日：2016-06-14
Inventor： Yoshikazu Katoh
CPC classification number: H04L9/3278 , G11C7/24 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0059 , G11C2213/32 , H01L45/08 , H01L45/1233 , H01L45/146
Abstract: A non-volatile memory device according to an aspect of the present disclosure includes a memory array that includes non-volatile memory cells; a read circuit that, in operation, selects, from the memory array, non-volatile memory cells corresponding to one of resistance value ranges, and obtains pieces of resistance value information about resistance values of the selected non-volatile memory cells; a computation circuit that, in operation, calculates a binarization reference value by using the pieces of resistance value information; and an identification information generation circuit that, in operation, generates individual identification information. The read circuit, in operation, obtains first digital data in accordance with relationships between each of the pieces of resistance value information and the binarization reference value. The identification information generation circuit, in operation, obtains second digital data uncorrelated with the resistance values, and generates the individual identification information by using the first digital data and the second digital data.
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公开(公告)号：US09921975B2
公开(公告)日：2018-03-20
申请号：US14685038
申请日：2015-04-13
Inventor： Yoshikazu Katoh , Takuji Maeda , Shinji Inoue , Masato Suto
CPC classification number: G06F12/1408 , G06F21/31 , G06F21/73 , G06F21/79 , G06F2212/1052 , G06F2221/2107 , G09C1/00 , G11C7/1006 , G11C13/0007 , G11C13/0069 , G11C2013/0083 , H04L2209/12
Abstract: A cryptographic processing device comprises a cipher control circuit operative to execute at least one of encryption of plaintext data and decryption of ciphertext data on the basis of conversion parameter data; and a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including the conversion parameter data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.
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Patent Agency Ranking
公开(公告)号：US09842645B2
公开(公告)日：2017-12-12
申请号：US15450648
申请日：2017-03-06
Inventor： Hiroyuki Tezuka , Yoshikazu Katoh
CPC classification number: G11C13/004 , G06F3/061 , G06F3/0625 , G06F3/0653 , G06F3/0679 , G11C13/0026 , G11C13/0061 , G11C13/0097 , G11C2213/79
Abstract: A nonvolatile memory device comprises: a nonvolatile memory; a resistance-time converter that outputs an end signal at timing according to a resistance value of the nonvolatile memory; and a time-digital converter that measures the time from input of a start signal to input of the end signal and converts the measured time into a digital value. The time-digital converter includes: a ring delay circuit that includes delay elements connected in a ring configuration; a counter circuit that counts the number of times of a rising edge or a falling edge in output of one of the delay elements; a first memory circuit that stores, based on the end signal, outputs of the delay elements as first data; and a second memory circuit that stores, based on the end signal, a count value of the counter circuit as second data.
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公开(公告)号：US09640238B2
公开(公告)日：2017-05-02
申请号：US14711785
申请日：2015-05-14
Inventor： Satoru Ogasahara , Yuhei Yoshimoto , Yoshikazu Katoh
CPC classification number: G11C11/16 , G11C11/5685 , G11C13/0007 , G11C13/0035 , G11C13/004 , G11C29/06 , G11C29/36 , G11C2013/0054 , G11C2211/5644
Abstract: A data generating device includes: a memory cell array including a plurality of memory cells; a read circuit operative to obtain a plurality of resistance value information pieces from the plurality of memory cells; and a data generator circuit operative to set a condition on the basis of the plurality of resistance value information pieces, and generating data by allocating, on the basis of the condition, the plurality of resistance value information pieces into a plurality of sets which respectively correspond to a plurality of values constituting the data. Each of the plurality of memory cells has a characteristic where, when in a variable state, a resistance value thereof reversibly changes between a plurality of variable resistance value ranges in accordance with an electric stress applied.
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8.发明授权Semiconductor device including memory cell and sense amplifer, and IC card including semiconductor device 有权包括存储单元和感测放大器的半导体器件，以及包括半导体器件的IC卡公开(公告)号：US09543007B2
公开(公告)日：2017-01-10
申请号：US15166152
申请日：2016-05-26
Inventor： Ryotaro Azuma , Yoshikazu Katoh
IPC: G11C11/419 , G11C7/14 , G11C7/06 , G11C7/22 , G11C13/00
CPC classification number: G11C13/004 , G11C7/06 , G11C7/067 , G11C7/14 , G11C13/0002 , G11C13/0007 , G11C13/0061 , G11C2013/0054 , G11C2207/066 , G11C2207/068 , G11C2213/79
Abstract: A semiconductor device includes a memory cell; circuitry that generates a reference voltage; and a sense amplifier including a first input terminal electrically connected to the memory cell, and a second input terminal electrically connected to the circuitry. The sense amplifier obtains a value in correlation with a resistance value of the memory cell based on a comparison between a sense voltage applied to the first input terminal and the reference voltage applied to the second input terminal. The sense voltage changes at a speed in correlation with the resistance value of the memory cell. In at least part of a period during which the sense voltage changes, the circuitry causes the reference voltage to change in a direction opposite to a direction in which the sense voltage changes.
Abstract translation: 半导体器件包括存储单元; 产生参考电压的电路; 以及读出放大器，包括电连接到存储单元的第一输入端子和电连接到该电路的第二输入端子。 感测放大器基于施加到第一输入端子的感测电压和施加到第二输入端子的参考电压之间的比较，获得与存储器单元的电阻值相关的值。 感测电压以与存储器单元的电阻值相关的速度变化。 在感测电压变化的周期的至少一部分期间，电路使得参考电压在与感测电压变化的方向相反的方向上改变。
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公开(公告)号：US10574639B2
公开(公告)日：2020-02-25
申请号：US15595976
申请日：2017-05-16
Inventor： Yoshikazu Katoh
Abstract: An authentication apparatus includes: a combination information generator that generates first combination information indicating a combination of physical characteristics of at least two of first elements included in a first semiconductor device; a group identification information generator that generates first group identification information based on the combination of the physical characteristics of the at least two of the first elements, the first group identification information being for identifying the first semiconductor device as belonging to a same group as another semiconductor device manufactured in a same process; a transmitter that transmits the first combination information to an authentication partner; a receiver that receives second group identification information that the authentication partner generates in accordance with the first combination information; and an information verifier that compares the first group identification information with the second group identification information.
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公开(公告)号：US10559051B2
公开(公告)日：2020-02-11
申请号：US15595979
申请日：2017-05-16
Inventor： Yoshikazu Katoh
Abstract: An image forgery protection apparatus comprises: one or more memories; and circuitry. The circuitry generates challenge data which change with lapse of time at least in a predetermined period. The circuitry generates a unique response which changes with lapse of time, the unique response corresponding to the challenge data on a basis of a physically unclonable function. The circuitry changes subject image data correspondingly to the unique response, the subject image data obtained by capturing an image of a subject.
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