公开(公告)号：US20230386978A1

公开(公告)日：2023-11-30

申请号：US18248990

申请日：2021-08-25

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masayuki KURODA ,  Takahiro SATO ,  Manabu YANAGIHARA ,  Hideyuki OKITA ,  Masahiro HIKITA

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L27/02 ,  H01L23/495

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L27/0255 ,  H01L23/4952 ,  H01L23/49562

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; finger-shaped source electrodes on the second nitride semiconductor layer; finger-shaped drain electrodes disposed so as to be spaced apart from the source electrodes; and finger-shaped gate electrodes respectively disposed between the source electrodes and the drain electrodes. The gate electrodes are electrically connected, via a first gate integrated wiring, a plurality of second gate integrated wirings and a third gate integrated wiring, to gate pads located on one or both ends of the third gate integrated wiring. A plurality of source pads and the plurality of second gate integrated wirings are formed alternately in a first direction perpendicular to the longitudinal direction of the gate electrodes.

公开(公告)号：US20230361179A1

公开(公告)日：2023-11-09

申请号：US18246280

申请日：2021-08-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu YANAGIHARA ,  Masayuki KURODA ,  Hiroto YAMAGIWA ,  Hideyuki OKITA ,  Masahiro HIKITA

IPC: H01L29/20 ,  H01L29/417 ,  H01L29/866 ,  H01L23/48 ,  H01L29/861

CPC classification number: H01L29/2003 ,  H01L29/41775 ,  H01L29/866 ,  H01L23/481 ,  H01L29/8613

Abstract: A nitride semiconductor device includes: a first active area surrounded by an isolation area; and the following electrodes above the first active area: a source electrode; a first gate electrode and a second gate electrode, one on either side of and spaced from the source electrode in a first direction in plan view; and at least one drain electrode located in a direction opposite the source electrode relative to the first gate electrode or the second gate electrode. The source electrode, the first gate electrode, the second gate electrode, and the at least one drain electrode each include a finger-shaped portion extending in a second direction perpendicular to the first direction in the plan view. A first dielectric film is disposed above the source electrode. The first gate electrode and the second gate electrode are electrically connected by a gate electrode joiner disposed above the first dielectric film.

公开(公告)号：US20180040706A1

公开(公告)日：2018-02-08

申请号：US15728141

申请日：2017-10-09

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Saichirou KANEKO ,  Hiroto YAMAGIWA ,  Ayanori IKOSHI ,  Masayuki KURODA ,  Manabu YANAGIHARA ,  Kenichiro TANAKA ,  Tetsuyuki FUKUSHIMA

IPC: H01L29/47 ,  H01L29/778 ,  H01L29/205 ,  H01L21/28 ,  H01L29/20 ,  H01L29/10 ,  H01L29/872 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/475 ,  H01L21/28 ,  H01L29/0619 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

公开(公告)号：US20160351676A1

公开(公告)日：2016-12-01

申请号：US15234775

申请日：2016-08-11

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Saichirou KANEKO ,  Hiroto YAMAGIWA ,  Ayanori IKOSHI ,  Masayuki KURODA ,  Manabu YANAGIHARA ,  Kenichiro TANAKA ,  Tetsuyuki FUKUSHIMA

IPC: H01L29/47 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778 ,  H01L29/872

CPC classification number: H01L29/475 ,  H01L21/28 ,  H01L29/0619 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.