公开(公告)号：US20250006798A1

公开(公告)日：2025-01-02

申请号：US18708941

申请日：2022-10-31

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki OKITA ,  Masahiro HIKITA ,  Yasuhiro UEMOTO

IPC: H01L29/20 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/207 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778

Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer provided over the substrate; a second nitride semiconductor layer that is on the first nitride semiconductor layer and includes a band gap larger than a band gap of the first nitride semiconductor layer; and a third nitride semiconductor layer that is on the second nitride semiconductor layer and includes a band gap larger than the band gap of the first nitride semiconductor layer. The second nitride semiconductor layer includes a damaged region in which an n-type impurity is selectively added by ion implantation. A diffusion region in which the n-type impurity is diffused is present in a vicinity of the damaged region. The nitride semiconductor device further includes: an ohmic electrode provided above the damaged region. The ohmic electrode is in ohmic contact with the diffusion region.

公开(公告)号：US20220302259A1

公开(公告)日：2022-09-22

申请号：US17637352

申请日：2020-08-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroto YAMAGIWA ,  Manabu YANAGIHARA ,  Takahiro SATO ,  Masahiro HIKITA ,  Hiroaki UENO ,  Yusuke KINOSHITA

IPC: H01L29/08 ,  H01L29/20 ,  H01L29/778 ,  H01L29/10

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer above the first nitride semiconductor layer and being greater than the first nitride semiconductor layer in band gap; and a first field-effect transistor including a first source electrode, a first drain electrode, and a first gate electrode that are above the second nitride semiconductor layer, the first source electrode and the first drain electrode being separated from each other, the first gate electrode being disposed between the first source electrode and the first drain electrode. The first field-effect transistor includes a third semiconductor layer that is above the second nitride semiconductor layer in part of a region between lower part of the first source electrode and the first gate electrode, and is separated from the first gate electrode. The third semiconductor layer and the first source electrode are electrically connected.

公开(公告)号：US20230386978A1

公开(公告)日：2023-11-30

申请号：US18248990

申请日：2021-08-25

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masayuki KURODA ,  Takahiro SATO ,  Manabu YANAGIHARA ,  Hideyuki OKITA ,  Masahiro HIKITA

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L27/02 ,  H01L23/495

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L27/0255 ,  H01L23/4952 ,  H01L23/49562

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; finger-shaped source electrodes on the second nitride semiconductor layer; finger-shaped drain electrodes disposed so as to be spaced apart from the source electrodes; and finger-shaped gate electrodes respectively disposed between the source electrodes and the drain electrodes. The gate electrodes are electrically connected, via a first gate integrated wiring, a plurality of second gate integrated wirings and a third gate integrated wiring, to gate pads located on one or both ends of the third gate integrated wiring. A plurality of source pads and the plurality of second gate integrated wirings are formed alternately in a first direction perpendicular to the longitudinal direction of the gate electrodes.

公开(公告)号：US20230361179A1

公开(公告)日：2023-11-09

申请号：US18246280

申请日：2021-08-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu YANAGIHARA ,  Masayuki KURODA ,  Hiroto YAMAGIWA ,  Hideyuki OKITA ,  Masahiro HIKITA

IPC: H01L29/20 ,  H01L29/417 ,  H01L29/866 ,  H01L23/48 ,  H01L29/861

CPC classification number: H01L29/2003 ,  H01L29/41775 ,  H01L29/866 ,  H01L23/481 ,  H01L29/8613

Abstract: A nitride semiconductor device includes: a first active area surrounded by an isolation area; and the following electrodes above the first active area: a source electrode; a first gate electrode and a second gate electrode, one on either side of and spaced from the source electrode in a first direction in plan view; and at least one drain electrode located in a direction opposite the source electrode relative to the first gate electrode or the second gate electrode. The source electrode, the first gate electrode, the second gate electrode, and the at least one drain electrode each include a finger-shaped portion extending in a second direction perpendicular to the first direction in the plan view. A first dielectric film is disposed above the source electrode. The first gate electrode and the second gate electrode are electrically connected by a gate electrode joiner disposed above the first dielectric film.

公开(公告)号：US20170148701A1

公开(公告)日：2017-05-25

申请号：US15427629

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ayanori IKOSHI ,  Masahiro HIKITA ,  Keiichi MATSUNAGA ,  Takahiro SATO ,  Manabu YANAGIHARA

IPC: H01L23/31 ,  H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/291 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/528 ,  H01L23/564 ,  H01L24/05 ,  H01L29/0684 ,  H01L29/417 ,  H01L29/812 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05023 ,  H01L2224/05144 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/48463 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/1033 ,  H01L2924/1304 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an electrode pad disposed on the first protective film; a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; and a first opening formed in part of the second protective film such that the upper surface of the electrode pad is exposed, wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of the periphery of the electrode pad and continuously surrounding the periphery of the electrode pad; and the second protective film is continuously to cover and contact part of the upper and side surfaces of the electrode pad, the upper and side surfaces of first projection, and the first protective film.

公开(公告)号：US20170117403A1

公开(公告)日：2017-04-27

申请号：US15399443

申请日：2017-01-05

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Hideyuki OKITA ,  Masahiro HIKITA ,  Hisayoshi MATSUO ,  Yasuhiro UEMOTO

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L29/0642 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/42316 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/7786

Abstract: A nitride semiconductor device including a substrate, a channel layer, a carbon-poor barrier layer having a recess, a carbon-rich barrier layer disposed over the recess and the carbon-poor barrier layer, and a gate electrode above the recess, wherein the carbon-poor and carbon-rich barrier layers have bandgaps larger than that of the channel layer, the upper surface of the carbon-rich barrier layer includes a first main surface including a source electrode and a drain electrode, and a bottom surface of a depression disposed along the recess, and side surfaces of the depression connecting the first main surface to the bottom surface of the depression, and among edges of the depression of the carbon-rich barrier layer which are boundaries between the first main surface and the side surfaces of the depression, the edge of the depression of the carbon-rich barrier layer closest to the drain electrode is covered with the gate electrode.

公开(公告)号：US20220320091A1

公开(公告)日：2022-10-06

申请号：US17630766

申请日：2020-08-21

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Manabu YANAGIHARA ,  Takahiro SATO ,  Hiroto YAMAGIWA ,  Masahiro HIKITA

IPC: H01L27/095 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778

Abstract: An integrated semiconductor device includes an Si substrate, and a high-side transistor and a low-side transistor which configure a half-bridge. A source electrode of a unit transistor configuring the high-side transistor and a drain electrode of a unit transistor configuring the low-side transistor are integrated as a common electrode.

公开(公告)号：US20240304630A1

公开(公告)日：2024-09-12

申请号：US18264561

申请日：2021-12-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroto YAMAGIWA ,  Manabu YANAGIHARA ,  Takahiro SATO ,  Masahiro HIKITA

IPC: H01L27/095 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L27/095 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786

Abstract: A semiconductor device includes third active regions that connect two finger-end portions of field effect transistors (FETs) spaced apart from each other, and includes, above the third active regions, portions of a third nitride semiconductor layer that includes P-type impurities.

公开(公告)号：US20240112909A1

公开(公告)日：2024-04-04

申请号：US18264202

申请日：2022-01-04

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hisayoshi MATSUO ,  Hideyuki OKITA ,  Masahiro HIKITA ,  Yasuhiro UEMOTO ,  Manabu YANAGIHARA

IPC: H01L21/02 ,  C30B25/18 ,  C30B29/40 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L21/02505 ,  C30B25/183 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/7786

Abstract: A nitride semiconductor epitaxial substrate includes: a Si substrate; a nitride semiconductor epitaxial layer disposed above the Si substrate; and a mixed crystal layer disposed between the Si substrate and the nitride semiconductor epitaxial layer, and containing Si and a group III metal element, the mixed crystal layer containing a high concentration of C. The mixed crystal layer has a concentration of at least 1.0×10+21 cm−3, and a transition metal element concentration of at most 5.0×10+16 cm−3.

公开(公告)号：US20230411506A1

公开(公告)日：2023-12-21

申请号：US18247705

申请日：2021-10-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideyuki OKITA ,  Manabu YANAGIHARA ,  Masahiro HIKITA

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/2003

Abstract: A nitride semiconductor device includes: a substrate; and a first nitride semiconductor layer, a second nitride semiconductor layer, and a third nitride semiconductor layer that are disposed above the substrate in the stated order. The first nitride semiconductor layer includes a recess. The second nitride semiconductor layer has a band gap larger than a band gap of the first nitride semiconductor layer and is disposed in a region other than the recess. The third nitride semiconductor layer has a band gap larger than the band gap of the first nitride semiconductor layer and covers the first nitride semiconductor layer and the second nitride semiconductor layer including an inner wall of the recess. A contact angle at which a side wall of the recess and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer meet ranges from 140° to less than 180°.