VARISTOR AND METHOD FOR PRODUCING SAME

    公开(公告)号:US20210358663A1

    公开(公告)日:2021-11-18

    申请号:US17286909

    申请日:2019-12-02

    Abstract: A varistor includes an effective layer having first and second surfaces opposite to each other, a first ineffective layer stacked on the first surface of the effective layer, a second ineffective layer stacked on the second surface of the effective layer, and an external electrode. The effective layer includes a ceramic layer having a polycrystalline structure including crystal particles exhibiting voltage nonlinear characteristics, and internal electrodes stacked alternately on the ceramic layer. The thickness of the second ineffective layer is equal to or more than 1.1 times a thickness of the first ineffective layer and equal to or smaller than 6 times the thickness of the first ineffective layer. This varistor has a small size and excellent surge resistance.

    PIEZOELECTRIC DEVICE AND METHOD FOR MANUFACTURING PIEZOELECTRIC DEVICE
    2.
    发明申请
    PIEZOELECTRIC DEVICE AND METHOD FOR MANUFACTURING PIEZOELECTRIC DEVICE 审中-公开
    压电元件及制造压电元件的方法

    公开(公告)号:US20160284979A1

    公开(公告)日:2016-09-29

    申请号:US15074005

    申请日:2016-03-18

    CPC classification number: H01L41/0815 H01L41/1876 H01L41/314 H01L41/319

    Abstract: A piezoelectric device includes a substrate, a lower electrode disposed above the substrate, a lower bonding layer disposed on the lower electrode, a piezoelectric layer containing a piezoelectric material disposed on an upper surface of the lower bonding layer, and an upper electrode disposed above the piezoelectric layer. The lower bonding layer includes an electrode material portion containing an electrode material of the lower electrode and a piezoelectric material portion containing a piezoelectric material. The electrode material portion and the piezoelectric material portion interdigitate with each other in the lower bonding layer.

    Abstract translation: 一种压电装置,包括基板,设置在基板上的下电极,设置在下电极上的下接合层,包含设置在下接合层的上表面上的压电材料的压电层和设置在下接合层上方的上电极 压电层。 下接合层包括含有下电极的电极材料的电极材料部分和包含压电材料的压电材料部分。 电极材料部分和压电材料部分在下粘合层中相互交错。

    VARISTOR ASSEMBLY
    3.
    发明申请

    公开(公告)号:US20220020512A1

    公开(公告)日:2022-01-20

    申请号:US17299774

    申请日:2019-12-02

    Abstract: Provided is a varistor assembly capable of achieving good surge breakdown voltage while suppressing capacitance. The varistor assembly is obtained by connecting a plurality of varistor elements in parallel. Each varistor element includes: a sintered body obtained by sintering a laminate in which varistor layers and internal electrodes are alternately laminated; and a pair of external electrodes provided in a state where the internal electrodes are alternately connected on at least both end faces of this sintered body. Varistor element includes at least a plurality of first group varistor elements in which a value obtained by dividing a surface area of the sintered body by a volume of the sintered body is 1.9 mm−1 or more.

    POWER STORAGE DEVICE
    5.
    发明申请

    公开(公告)号:US20210351435A1

    公开(公告)日:2021-11-11

    申请号:US17384845

    申请日:2021-07-26

    Abstract: The present disclosure provides a surface-mount power storage device. A power storage device of the present disclosure includes a solid electrolyte layer; a coating layer that coats a surface of the solid electrolyte layer; a first internal electrode disposed inside the solid electrolyte layer; a first external electrode disposed outside of the solid electrolyte layer and electrically connected to the first internal electrode; a second internal electrode disposed inside the solid electrolyte layer; and a second external electrode disposed outside of the solid electrolyte layer and electrically connected to the second internal electrode. The coating layer has a conductivity less than a conductivity of the solid electrolyte layer.

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