公开(公告)号：US06823402B2

公开(公告)日：2004-11-23

申请号：US10001152

申请日：2001-11-14

申请人： Patrick J. Smith ,  Jay B. Reimer ,  Ramesh A. Iyer ,  Henry D. Nguyen

发明人： Patrick J. Smith ,  Jay B. Reimer ,  Ramesh A. Iyer ,  Henry D. Nguyen

IPC分类号： G06F1328

CPC分类号： G06F13/1652 ,  H04L29/06 ,  H04L69/324

摘要： In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem. In response to a predetermined condition, the signal groups are forwarded to the identified digital signal processor subsystem. The channel block unit, in response to preselected signal groups, can direct the packet to a digital signal processor subsystem that is different from the digital signal processor subsystem identified by the address signal group.

摘要翻译： 在包括多个数字信号处理器子系统的数据处理系统中，所选择的外围组件由数字信号处理器子系统共享。 特别地，高级数据链路控制器由子系统共享。 当共享高级数据链路控制器接收到分组时，数据信号组被处理并放置在临时存储单元中。 接收到的分组的地址信号组被应用于信道块单元，在该信道块单元中，识别分组被引导到的数字信号处理器子系统，并产生与所识别的数字信号处理器子系统对应的INTERRUPT信号。 INTERRUPT信号被应用于开关。 从临时存储单元接收信号组的开关将信号组引导到与所识别的信号处理子系统相关联的信道中的缓冲存储器。 响应于预定条件，信号组被转发到所识别的数字信号处理器子系统。 响应于预选信号组，信道块单元可以将分组引导到与由地址信号组识别的数字信号处理器子系统不同的数字信号处理器子系统。

公开(公告)号：US07054958B2

公开(公告)日：2006-05-30

申请号：US10001153

申请日：2001-11-14

申请人： Ramesh A. Iyer ,  Henry D. Nguyen ,  Patrick J. Smith ,  Jay B. Reimer

发明人： Ramesh A. Iyer ,  Henry D. Nguyen ,  Patrick J. Smith ,  Jay B. Reimer

IPC分类号： G06F13/28

CPC分类号： G06F13/387

摘要： In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed. An abort signal is generated when a signal group for a packet being processed by the high level data link controller is not available in a timely manner.

公开(公告)号：US06892266B2

公开(公告)日：2005-05-10

申请号：US10008696

申请日：2001-11-08

申请人： Jay B. Reimer ,  Harland Glenn Hopkins ,  Tai H. Nguyen ,  Yi Luo ,  Kevin A. McGonagle ,  Jason A. Jones ,  Duy Q. Nguyen ,  Patrick J. Smith

发明人： Jay B. Reimer ,  Harland Glenn Hopkins ,  Tai H. Nguyen ,  Yi Luo ,  Kevin A. McGonagle ,  Jason A. Jones ,  Duy Q. Nguyen ,  Patrick J. Smith

IPC分类号： G06F9/30 ,  G06F13/16 ,  G06F13/28 ,  G06F13/362 ,  G06F15/78 ,  G06F13/14

CPC分类号： G06F13/28

摘要： A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

摘要翻译： 公开了具有多个DMA控制器的DSP设备，其全局DMA访问DSP设备中的所有易失性存储器资源。 在优选实施例中，每个DMA控制器耦合到每个存储器总线，并且被配置为控制每个存储器总线。 存储器总线多路复用器可以耦合在子系统存储器总线和每个DMA控制器之间，并且仲裁器可以用于设置存储器总线多路复用器，以便允许任何一个DMA控制器来控制存储器总线。 存储器总线也可以经由存储器总线多路复用器由主机端口接口来控制。 循环仲裁技术用于提供每个控制器和主机端口接口公平地访问存储器总线。 这种方法可以有利地提供使用DMA控制器将数据从一个地方传输到另一个地方的增加的灵活性，只有最小的复杂性增加。

公开(公告)号：US06691216B2

公开(公告)日：2004-02-10

申请号：US10004492

申请日：2001-10-24

申请人： Kenneth C. Kelly ,  Irvinderpal S. Ghai ,  Jay B. Reimer ,  Tai Huu Nguyen ,  Harland Glenn Hopkins ,  Yi Luo ,  Jason A. T. Jones ,  Dan K. Bui ,  Patrick J. Smith ,  Kevin A. McGonagle

发明人： Kenneth C. Kelly ,  Irvinderpal S. Ghai ,  Jay B. Reimer ,  Tai Huu Nguyen ,  Harland Glenn Hopkins ,  Yi Luo ,  Jason A. T. Jones ,  Dan K. Bui ,  Patrick J. Smith ,  Kevin A. McGonagle

IPC分类号： G06F1578

CPC分类号： G06F9/3802 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3891 ,  G06F15/786 ,  Y02D10/13

摘要： A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because each of the program cores typically executes the same software program, memory requirements may be reduced by having multiple processor cores share only a single copy of the software. Accordingly, a program memory couples to each of the processor cores by a corresponding instruction bus. Preferably the program memory services two or more instruction requests in each clock cycle. Data is preferably stored in separate memory arrays local to the processor core subsystems and accessible by the processor cores via a dedicated data bus. In one specific implementation, the program memory includes a wrapper that can perform one memory access in the first half of each clock cycle and a second memory access in the second half of each clock cycle. A designated set of instruction buses is allowed to arbitrate for only the first access, and the remaining instruction buses are allowed to arbitrate for only the second access. In this manner, a reduction in on-board memory requirements and associated power consumption may be advantageously reduced.

摘要翻译： 多核DSP设备包括共享程序存储器以消除冗余，从而减小DSP设备的尺寸和功耗。 由于每个程序内核通常执行相同的软件程序，因此可以通过使多个处理器核心共享该软件的单个副本来减少内存需求。 因此，程序存储器通过相应的指令总线耦合到每个处理器核心。 优选地，程序存储器在每个时钟周期中服务两个或更多个指令请求。 数据优选地存储在处理器核心子系统本地的分开的存储器阵列中，并且可经由专用数据总线由处理器核心访问。 在一个具体实现中，程序存储器包括一个包装器，其可以在每个时钟周期的前半部分中执行一个存储器访问，并且在每个时钟周期的后半部分中执行第二存储器访问。 允许指定的一组指令总线仅对第一次访问进行仲裁，并且允许剩余的指令总线仅对第二次访问进行仲裁。 以这种方式，可以有利地减少车载存储器要求的降低和相关联的功率消耗。

公开(公告)号：US07570646B2

公开(公告)日：2009-08-04

申请号：US09964158

申请日：2001-09-26

申请人： Martin Li ,  Jay B. Reimer ,  Shakuntala Anjanaiah ,  Natarajan Seshan ,  Patrick J. Smith

发明人： Martin Li ,  Jay B. Reimer ,  Shakuntala Anjanaiah ,  Natarajan Seshan ,  Patrick J. Smith

IPC分类号： H04L12/28

CPC分类号： G06F13/4004 ,  G06F1/24 ,  G06F13/28 ,  G06F13/385

摘要： A slave interface unit controls the exchange of data between a master processing unit and a plurality of slave processing units operating in the asynchronous transfer mode (ATM) of operation. The ATM slave interface unit has a receive unit and a transmit unit that exchange data cells and control signals with the ATM master processing unit. The receive unit and the transmit unit are coupled to a receive buffer storage unit and a transmit buffer storage unit, respectively. The receive buffer storage unit and the transmit buffer storage unit exchange data and control signals with the direct memory access unit. The ATM slave interface unit includes a configuration interface unit having a register that identifies the location in the data cell where the destination address is located and relates the destination address to the particular processing unit or memory location. The receive buffer unit uses the information in the register to determine the destination of the data cell.

摘要翻译： 从接口单元控制主处理单元和以异步传送模式（ATM）操作的多个从属处理单元之间的数据交换。 ATM从接口单元具有接收单元和与ATM主处理单元交换数据信元和控制信号的发送单元。 接收单元和发送单元分别耦合到接收缓冲存储单元和发送缓冲存储单元。 接收缓冲存储单元和发送缓冲存储单元与直接存储器存取单元交换数据和控制信号。 ATM从接口单元包括配置接口单元，其具有标识目的地址所在的数据单元中的位置的寄存器，并将目的地地址与特定处理单元或存储器位置相关联。 接收缓冲器单元使用寄存器中的信息来确定数据单元的目的地。

公开(公告)号：US20110065556A1

公开(公告)日：2011-03-17

申请号：US12950215

申请日：2010-11-19

申请人： Scott W. Middleton ,  Mark R. Sinclair ,  Brian R. O'Hagan ,  Patrick H. Wnek ,  Terrence P. Lafferty ,  Peter W. Blaas ,  Kevin J. Hjort ,  Patrick J. Smith

发明人： Scott W. Middleton ,  Mark R. Sinclair ,  Brian R. O'Hagan ,  Patrick H. Wnek ,  Terrence P. Lafferty ,  Peter W. Blaas ,  Kevin J. Hjort ,  Patrick J. Smith

IPC分类号： B31B49/00

CPC分类号： B29C45/14336 ,  B29C45/14065 ,  B29C45/14467 ,  B29C45/14508 ,  B29C45/1671 ,  B29C2045/0027 ,  B29C2045/14918 ,  B29L2031/712 ,  B31B50/592 ,  B65D1/48 ,  B65D5/209 ,  B65D5/445 ,  B65D43/162 ,  B65D43/169 ,  B65D77/2016 ,  B65D77/2032 ,  B65D77/208 ,  B65D77/2088 ,  B65D77/245 ,  B65D81/3453 ,  B65D2581/344 ,  B65D2581/3498

摘要： A tray or container which may be hermetically sealed having a flange, rim, handle, rib, bottom surface, sidewall, or other portion that is encapsulated by or formed from injection molded material

摘要翻译： 可以气密密封的托盘或容器，其具有凸缘，边缘，手柄，肋，底表面，侧壁或其它部分，其被注射成型材料封装或由其注塑成型

公开(公告)号：US06789183B1

公开(公告)日：2004-09-07

申请号：US09670664

申请日：2000-09-27

申请人： Patrick J. Smith ,  Jason A. Jones ,  Kevin A. McGonagle

发明人： Patrick J. Smith ,  Jason A. Jones ,  Kevin A. McGonagle

IPC分类号： G06F1328

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： In a digital processing unit having a plurality of digital signal processors, a first digital signal processor can request a direct transfer of a signal group stored in the memory unit of a second digital signal processor. In order to insure that the second digital signal is active, a control signal is generated by the direct memory access controller of the first digital signal processor. The control signal is applied the directly to the memory access controller of the second digital signal processor. When the second digital signal processor is in an IDLE mode, the control signal activates the second digital signal processor.

摘要翻译： 在具有多个数字信号处理器的数字处理单元中，第一数字信号处理器可以请求存储在第二数字信号处理器的存储单元中的信号组的直接传送。 为了确保第二数字信号有效，控制信号由第一数字信号处理器的直接存储器存取控制器产生。 控制信号被直接施加到第二数字信号处理器的存储器存取控制器。 当第二数字信号处理器处于空闲模式时，控制信号激活第二数字信号处理器。

公开(公告)号：US4956644A

公开(公告)日：1990-09-11

申请号：US417124

申请日：1989-10-04

申请人： Ronald S. Leahy ,  Patrick J. Smith ,  Scott R. Bullock

发明人： Ronald S. Leahy ,  Patrick J. Smith ,  Scott R. Bullock

IPC分类号： H04B1/713 ,  H04B1/715

CPC分类号： H04B1/715 ,  H04B1/713 ,  H04B2001/7152

摘要： A signal detector for receiving a wide band (W) of frequency-hopped signals which channelizes the incoming signals, via filter banks into a plurality (L) of channels. Magnitude squaring circuits in each channel generate a "power" estimate which is compared to a preset threshold value by threshold-quantizer units that produce a positive voltage (=1) if the threshold is exceeded. After summation of all the channels, the direct sequence (DS) signal component and noise component are processed so that a DC voltage is produced if a frequency-hop signal (FH) is present which is greater in value than when the signal is not present. Thus the DC signal indicates whether the FH signal is present or absent.

摘要翻译： 一种信号检测器，用于接收频带跳频信号的宽带（W），其将输入信号通过滤波器组分频成多个（L）个信道。 每个通道中的幅度平方电路产生“功率”估计，其通过产生正电压（= 1）的阈值量化器单元与预设阈值进行比较，如果超过阈值。 在所有通道的总和之后，处理直接序列（DS）信号分量和噪声分量，使得如果存在与不存在信号时相比值大的频率跳跃信号（FH），则产生直流电压 。 因此，DC信号指示FH信号是存在还是不存在。

公开(公告)号：US4947361A

公开(公告)日：1990-08-07

申请号：US250795

申请日：1988-09-28

申请人： Patrick J. Smith ,  Scott R. Bullock ,  Jeffery Mac Thornock

发明人： Patrick J. Smith ,  Scott R. Bullock ,  Jeffery Mac Thornock

IPC分类号： H03H21/00

CPC分类号： H03H21/0012

摘要： A narrowband parameter estimator circuit is described which can be used to estimate the frequency and the relative power of narrowband interference tones which reside in a wideband information signal. A two-weight adaptive filter with a phase/frequency-lock loop circuit works in conjunction with a stepped synthesizer to lock onto the individual narrowband interference tones. A lock-detect circuit signals a digital logic unit to record the frequency of the stepped synthesizer and to measure the power in the adaptive filter output signal. This same output signal is used to cancel the unwanted tone in the wideband information signal being transmitted.

摘要翻译： 描述了可以用于估计位于宽带信息信号中的窄带干扰音调的频率和相对功率的窄带参数估计器电路。 具有相位/频率锁定环路电路的双重自适应滤波器与阶梯式合成器一起工作，以锁定到各个窄带干扰音调上。 锁定检测电路向数字逻辑单元发出信号以记录阶梯式合成器的频率并测量自适应滤波器输出信号中的功率。 该相同的输出信号用于消除所发送的宽带信息信号中的不需要的音调。

公开(公告)号：US10010195B2

公开(公告)日：2018-07-03

申请号：US13324460

申请日：2011-12-13

申请人： Patrick J. Smith ,  Andy L. Kirkpatrick ,  Michael R. Kilgore ,  David G. Honan

发明人： Patrick J. Smith ,  Andy L. Kirkpatrick ,  Michael R. Kilgore ,  David G. Honan

IPC分类号： A47F1/10

CPC分类号： A47F1/10 ,  A47F2001/103

摘要： A configuration of disposable cutlery comprises a plurality of disposable cutlery pieces suitable for loading in a disposable cutlery dispenser, wherein the plurality is not constrained by a cartridge when loaded into the cutlery dispenser, wherein the plurality is in a substantially unfanned orientation after loading of the plurality into a cutlery dispenser, and wherein each piece comprises a solid handle.