-
公开(公告)号：US07225097B2
公开(公告)日：2007-05-29
申请号：US11191418
申请日：2005-07-28
IPC分类号： G06F17/00
CPC分类号： G11C29/50 , G11C29/028 , G11C2029/0407 , G11C2029/0409 , G11C2029/4402 , G11C2207/2254
摘要： In a first aspect, a first method is provided for adjusting memory system calibration. The first method includes the steps of (1) while in a first operating state, calibrating the memory system using a first amount of calibration data so that functional data may be read from and written to memory of the memory system; and (2) while in a second operating state, calibrating the memory system using a second amount of calibration data so that functional data may be read from and written to the memory, wherein the second amount of calibration data is smaller than the first amount of calibration data. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种用于调整存储器系统校准的方法。 第一种方法包括以下步骤：（1）在第一操作状态下，使用第一量的校准数据校准存储器系统，使得功能数据可以从存储器系统的存储器中读出并写入存储器系统; 和（2）在第二操作状态下，使用第二量的校准数据校准存储器系统，使得功能数据可以从存储器中读出并写入存储器，其中第二量的校准数据小于第一量的校准数据 校准数据。 提供了许多其他方面。
-
公开(公告)号：US07669028B2
公开(公告)日：2010-02-23
申请号：US11348884
申请日：2006-02-07
CPC分类号： G06F13/1689
摘要： Embodiments of the present invention optimize data bandwidth across an asynchronous buffer in a system with a variable clock domain. A move signal may be asserted to transfer data associated with a command into the asynchronous buffer. After the data has been moved into the buffer, an acknowledge signal may indicate that the transfer is complete. A launch signal may transfer the data in the asynchronous buffer to memory. Embodiments of the present invention allow the processing of a next command to begin at the earliest possible time while data associated with a previous command is being transferred into and out of the buffer, thereby increasing throughput and improving performance.
摘要翻译： 本发明的实施例通过具有可变时钟域的系统中的异步缓冲器来优化数据带宽。 可以断言移动信号将与命令相关联的数据传送到异步缓冲器。 数据移入缓冲区后，确认信号可能表示传输完成。 发射信号可以将异步缓冲器中的数据传输到存储器。 本发明的实施例允许下一个命令的处理在尽可能早的时间开始，而与先前命令相关联的数据正被传入和传出缓冲器，从而提高吞吐量并提高性能。
-
公开(公告)号：US08213428B2
公开(公告)日：2012-07-03
申请号：US10625954
申请日：2003-07-24
IPC分类号： H04L12/56
CPC分类号： H04L49/3009
摘要： A method is provided for address mapping in a network processor. The method includes the steps of (1) determining a port number of a port that receives a data cell; (2) determining a virtual path identifier and a virtual channel identifier for the data cell; and (3) creating a first index based on at least one of the port number, the virtual path identifier and the virtual channel identifier. The method further includes (1) accessing one of a plurality of entries stored in a first on-chip memory using the first index; (2) creating a second index based on the accessed entry of the first on-chip memory; and (3) accessing an entry of a second memory based on the second index. Numerous other aspects are provided.
摘要翻译： 提供了一种用于网络处理器中的地址映射的方法。 该方法包括以下步骤：（1）确定接收数据信元的端口的端口号; （2）确定数据信元的虚拟路径标识符和虚拟信道标识符; 以及（3）基于端口号，虚拟路径标识符和虚拟信道标识符中的至少一个来创建第一索引。 该方法还包括：（1）使用第一索引访问存储在第一片上存储器中的多个条目中的一个; （2）基于所访问的第一片上存储器的条目创建第二索引; 和（3）基于第二索引访问第二存储器的条目。 提供了许多其他方面。
-
4.发明授权Implementing pointer and stake model for frame alteration code in a network processor 失效在网络处理器中实现帧更改代码的指针和投注模型公开(公告)号：US08170024B2
公开(公告)日：2012-05-01
申请号：US11934810
申请日：2007-11-05
申请人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
发明人： Kerry Christopher Imming , John David Irish , Joseph Franklin Logan , Tolga Ozguner , Michael Steven Siegel
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90
摘要： A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.
摘要翻译： 提供了一种方法，装置和计算机程序产品，用于在网络处理器中实现用于帧改变码的指针和拍摄模型。 为选择用于发送的分组提供当前指针和分支。 保持当前指针用于跟踪分组中帧更改操作的当前位置。 保留该批次用于跟踪该分组中的帧更改操作的当前报头的开始。 当前指针由帧改变代码指令使用以指定相对于当前指针的操作序列。 指定的帧改变序列在代码大小方面是紧凑的，以便在小的字节窗口内对数据进行操作。 高级指针指令允许当前和指针指针以任意数量的字节进入数据包。
-
5.发明授权公开(公告)号：US07925823B2
公开(公告)日：2011-04-12
申请号：US11875469
申请日：2007-10-19
IPC分类号： G06F12/00
CPC分类号： G11C29/02 , G11C29/022 , G11C29/028
摘要： A mechanism is provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.
摘要翻译： 提供了重用功能数据缓冲器的机制。 使用极限数据速率（XDR™）动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。 为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。 然而，发送和接收校准有不同的程序和要求。 因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。
-
6.发明授权Managing write-to-read turnarounds in an early read after write memory system 有权在写入内存系统之后的早期读取中管理写入阅读的周转时间公开(公告)号：US07752379B2
公开(公告)日：2010-07-06
申请号：US12349240
申请日：2009-01-06
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
CPC分类号： G06F13/161 , G06F13/1647
摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
摘要翻译： 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信号 一个奇怪的DRAM银行。
-
公开(公告)号：US20070027650A1
公开(公告)日：2007-02-01
申请号：US11191418
申请日：2005-07-28
申请人： Paul Ganfield , Brian McKevett , Tolga Ozguner
发明人： Paul Ganfield , Brian McKevett , Tolga Ozguner
CPC分类号： G11C29/50 , G11C29/028 , G11C2029/0407 , G11C2029/0409 , G11C2029/4402 , G11C2207/2254
摘要： In a first aspect, a first method is provided for adjusting memory system calibration. The first method includes the steps of (1) while in a first operating state, calibrating the memory system using a first amount of calibration data so that functional data may be read from and written to memory of the memory system; and (2) while in a second operating state, calibrating the memory system using a second amount of calibration data so that functional data may be read from and written to the memory, wherein the second amount of calibration data is smaller than the first amount of calibration data. Numerous other aspects are provided.
-
8.发明申请公开(公告)号：US20060129754A1
公开(公告)日：2006-06-15
申请号：US10992378
申请日：2004-11-18
申请人： Mark Bellows , Kent Haselhorst , Paul Ganfield , Tolga Ozguner
发明人： Mark Bellows , Kent Haselhorst , Paul Ganfield , Tolga Ozguner
IPC分类号： G06F12/00
CPC分类号： G11C29/02 , G11C29/022 , G11C29/028
摘要： A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.
摘要翻译： 提供了一种方法，装置和计算机程序来重用功能数据缓冲器。 使用极限数据速率（XDR（TMDR））动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。 为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。 然而，发送和接收校准有不同的程序和要求。 因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。
-
公开(公告)号：US20060123187A1
公开(公告)日：2006-06-08
申请号：US11002556
申请日：2004-12-02
申请人： Mark Bellows , Kent Haselhorst , Ryan Heakendorf , Paul Ganfield , Tolga Ozguner
发明人： Mark Bellows , Kent Haselhorst , Ryan Heakendorf , Paul Ganfield , Tolga Ozguner
IPC分类号： G06F12/00
CPC分类号： G06F13/1673
摘要： A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.
摘要翻译： 提供了一种方法，装置和计算机程序来解释存储在动态随机存取存储器（DRAM）写入缓冲器中的数据。 跟踪存储在DRAM写入缓冲器中的数据是困难的。 为了缓解困难，采用缓存行列表。 缓存行列表被保存在存储器控制器中，该存储器控制器被数据移动更新。 该列表允许轻松维护数据而不失一致性。
-
10.发明申请Method, apparatus, and computer program product for implementing pointer and stake model for frame alteration code in a network processor 失效方法，装置和计算机程序产品，用于实现网络处理器中帧改变代码的指针和投注模型公开(公告)号：US20050063415A1
公开(公告)日：2005-03-24
申请号：US10667024
申请日：2003-09-18
申请人： Kerry Imming , John Irish , Joseph Logan , Tolga Ozguner , Michael Siegel
发明人： Kerry Imming , John Irish , Joseph Logan , Tolga Ozguner , Michael Siegel
CPC分类号： H04L49/901 , H04L49/90
摘要： A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.
摘要翻译： 提供了一种方法，装置和计算机程序产品，用于在网络处理器中实现用于帧改变码的指针和拍摄模型。 为选择用于发送的分组提供当前指针和分支。 保持当前指针用于跟踪分组中帧更改操作的当前位置。 保留该批次用于跟踪该分组中的帧更改操作的当前报头的开始。 当前指针由帧改变代码指令使用以指定相对于当前指针的操作序列。 指定的帧改变序列在代码大小方面是紧凑的，以便在小的字节窗口内对数据进行操作。 高级指针指令允许当前和指针指针以任意数量的字节进入数据包。
-
-
-
-
-
-
-
-
-
搜索结果
44 条记录 (耗时 0.037 秒)
