Feedback loop with adjustable bandwidth
    1.
    发明授权
    Feedback loop with adjustable bandwidth 有权
    具有可调节带宽的反馈回路

    公开(公告)号:US08107901B2

    公开(公告)日:2012-01-31

    申请号:US09933364

    申请日:2001-08-20

    CPC分类号: H03F1/083

    摘要: A feedback loop with an adjustable closed loop frequency response. The feedback loop contains adjustable pole (212, 213) and adjustable zero elements (220,221) for changing the pole and/or zero locations in the feedback loop's loop frequency response thereby changing the closed loop frequency response of the feedback loop. In one embodiment, the feedback loop is a Cartesian feedback loop suitable for use in a radio transmitter.

    摘要翻译: 具有可调节闭环频率响应的反馈回路。 反馈环路包括可调节极点(212,213)和可调零元件(220,221),用于改变反馈回路​​环路频率响应中的极点和/或零点位置,从而改变反馈回路​​的闭环频率响应。 在一个实施例中,反馈回路是适用于无线电发射机的笛卡尔反馈回路。

    Method and apparatus for generating phase shifted local oscillator signals for a feedback loop on a transmitter
    2.
    发明授权
    Method and apparatus for generating phase shifted local oscillator signals for a feedback loop on a transmitter 有权
    用于产生发射机中的反馈回路的相移本地振荡器信号的方法和装置

    公开(公告)号:US08059777B2

    公开(公告)日:2011-11-15

    申请号:US11941281

    申请日:2007-11-16

    IPC分类号: H03D3/24

    摘要: A transmitter is provided with a local oscillator (LO) processing unit to maintain stability in the transmitter's feedback loop. The LO processing unit includes at least one delay locked loop (DLL) and a programmable divider to generate phase shifted LO signals for adjusting a loop phase of the feedback loop in the transmitter. The generated phase shifted LO signals are of both a coarse and fine phase shifted nature. The adjustability and control of the coarse and fine phase shifting of the LO signals maintains linearity in the transmitter feedback loop.

    摘要翻译: 发射机设有本地振荡器(LO)处理单元,以保持发射机反馈环路的稳定性。 LO处理单元包括至少一个延迟锁定环(DLL)和可编程分频器,以产生相移的LO信号,用于调整发射机中的反馈回路的环路相位。 产生的相移的LO信号既具有粗调和精细的相移特性。 LO信号的粗调和精细相移的可调性和控制在发射机反馈环路中保持线性。

    METHOD AND APPARATUS FOR GENERATING PHASE SHIFTED LOCAL OSCILLATOR SIGNALS FOR A FEEDBACK LOOP ON A TRANSMITTER
    3.
    发明申请
    METHOD AND APPARATUS FOR GENERATING PHASE SHIFTED LOCAL OSCILLATOR SIGNALS FOR A FEEDBACK LOOP ON A TRANSMITTER 有权
    用于在变送器中产生反相环路的相位偏移的本地振荡器信号的方法和装置

    公开(公告)号:US20090129446A1

    公开(公告)日:2009-05-21

    申请号:US11941281

    申请日:2007-11-16

    IPC分类号: H04B1/06

    摘要: A transmitter is provided with a local oscillator (LO) processing unit to maintain stability in the transmitter's feedback loop. The LO processing unit includes at least one delay locked loop (DLL) and a programmable divider to generate phase shifted LO signals for adjusting a loop phase of the feedback loop in the transmitter. The generated phase shifted LO signals are of both a coarse and fine phase shifted nature. The adjustability and control of the coarse and fine phase shifting of the LO signals maintains linearity in the transmitter feedback loop.

    摘要翻译: 发射机设有本地振荡器(LO)处理单元,以保持发射机反馈环路的稳定性。 LO处理单元包括至少一个延迟锁定环(DLL)和可编程分频器,以产生相移的LO信号,用于调整发射机中的反馈回路的环路相位。 产生的相移的LO信号既具有粗调和精细的相移特性。 LO信号的粗调和精细相移的可调性和控制在发射机反馈环路中保持线性。

    Apparatus and method for producing a plurality of output signals with
fixed phase relationships therebetween
    4.
    发明授权
    Apparatus and method for producing a plurality of output signals with fixed phase relationships therebetween 失效
    用于产生具有固定相位关系的多个输出信号的装置和方法

    公开(公告)号:US5930689A

    公开(公告)日:1999-07-27

    申请号:US957078

    申请日:1997-10-24

    摘要: An apparatus and method produce a plurality of output signals (917-921) with fixed phase relationships therebetween. The apparatus (900) includes a first signal generator (901), a second signal generator (903), and a signal processor (907). The first signal generator produces a first input signal (911) at a first frequency. The second signal generator produces a second input signal (915) at a second frequency, wherein the second frequency is an integer multiple of the first frequency. The signal processor receives the first and second input signals and produces a plurality of output signals (917-921) having fixed phase relationships therebetween at the first frequency, wherein the fixed phase relationships are based on the integer multiple and wherein each of the output signals has a single, determinate phase relative to the phase of the first input signal.

    摘要翻译: 一种装置和方法产生其间具有固定相位关系的多个输出信号(917-921)。 装置(900)包括第一信号发生器(901),第二信号发生器(903)和信号处理器(907)。 第一信号发生器以第一频率产生第一输入信号(911)。 第二信号发生器以第二频率产生第二输入信号(915),其中第二频率是第一频率的整数倍。 信号处理器接收第一和第二输入信号并产生在第一频率处具有固定相位关系的多个输出信号(917-921),其中固定相位关系基于整数倍,并且其中每个输出信号 具有相对于第一输入信号的相位的单个确定相位。

    Apparatus and method for producing a plurality of output signals with fixed phase relationships therebetween
    5.
    发明授权
    Apparatus and method for producing a plurality of output signals with fixed phase relationships therebetween 失效
    用于产生具有固定相位关系的多个输出信号的装置和方法

    公开(公告)号:US06253066B1

    公开(公告)日:2001-06-26

    申请号:US09283353

    申请日:1999-03-31

    IPC分类号: H01Q1112

    摘要: An apparatus and method produce a plurality of output signals (917-921) with fixed phase relationships therebetween. The apparatus (900) includes a first signal generator (901), a second signal generator (903), and a signal processor (907). The first signal generator produces a first input signal (911) at a first frequency. The second signal generator produces a second input signal (915) at a second frequency, wherein the second frequency is an integer multiple of the first frequency. The signal processor receives the first and second input signals and produces a plurality of output signals (917-921) having fixed phase relationships therebetween at the first frequency, wherein the fixed phase relationships are based on the integer multiple and wherein each of the output signals has a single, determinate phase relative to the phase of the first input signal.

    摘要翻译: 一种装置和方法产生其间具有固定相位关系的多个输出信号(917-921)。 装置(900)包括第一信号发生器(901),第二信号发生器(903)和信号处理器(907)。 第一信号发生器以第一频率产生第一输入信号(911)。 第二信号发生器以第二频率产生第二输入信号(915),其中第二频率是第一频率的整数倍。 信号处理器接收第一和第二输入信号并产生在第一频率处具有固定相位关系的多个输出信号(917-921),其中固定相位关系基于整数倍,并且其中每个输出信号 具有相对于第一输入信号的相位的单个确定相位。

    METHOD AND APPARATUS FOR A SYNTHESIZER ARCHITECTURE
    7.
    发明申请
    METHOD AND APPARATUS FOR A SYNTHESIZER ARCHITECTURE 审中-公开
    合成器结构的方法和装置

    公开(公告)号:US20140062605A1

    公开(公告)日:2014-03-06

    申请号:US13601488

    申请日:2012-08-31

    IPC分类号: H03L7/16

    摘要: A synthesizer architecture, responsive to a low noise reference signal from a discrete oscillator, provides a continuous periodic output with a period that is a fractional multiple of the low noise reference signal. One exemplary embodiment includes a phase detector providing a control signal to a selected one of a plurality of integrated voltage controlled oscillators (VCO), wherein the phase detector is a sub-harmonic continuous time sampling phase detector. Another exemplary embodiment includes a continuous fractional divider input to the phase detector in response to an output of the selected VCO. Yet another exemplary embodiment comprises an injection locked ring oscillator responsive to the low noise narrow band variable reference signal with a fractional output period.

    摘要翻译: 响应于来自离散振荡器的低噪声参考信号的合成器架构提供了具有低噪声参考信号的分数倍的周期的连续周期性输出。 一个示例性实施例包括相位检测器,其向多个集成压控振荡器(VCO)中的所选择的一个提供控制信号,其中相位检测器是次谐波连续时间采样相位检测器。 另一示例性实施例包括响应于所选择的VCO的输出的相位检测器的连续分数分频器输入。 另一个示例性实施例包括响应于具有小数输出周期的低噪声窄带可变参考信号的注入锁定环形振荡器。

    Broadband self adjusting quadrature signal generator and method thereof
    8.
    发明授权
    Broadband self adjusting quadrature signal generator and method thereof 有权
    宽带自调整正交信号发生器及其方法

    公开(公告)号:US08121215B2

    公开(公告)日:2012-02-21

    申请号:US11771005

    申请日:2007-06-29

    IPC分类号: H04L25/49

    CPC分类号: H03H17/08

    摘要: Low noise phase quadrature signals are generated after receiving a clock signal and adjusting the clock signal in response to a feedback signal to generate a phase adjusted clock signal. The clock signal and the phase adjusted clock signal are exclusive-ored to generate a frequency doubled signal. An in-phase local oscillator signal and a quadrature local oscillator signal are generated from the frequency doubled signal such that the in-phase local oscillator and the quadrature local oscillator signal are out-of-phase with each other. In addition, a phase relationship between the in-phase local oscillator signal and the quadrature local oscillator signal are detected, and the feedback signal is generated based upon the phase relationship between the in-phase local oscillator signal and the quadrature local oscillator signal.

    摘要翻译: 在接收到时钟信号并响应于反馈信号调整时钟信号以产生相位调整的时钟信号后,产生低噪声相位正交信号。 时钟信号和相位调整的时钟信号被异或以产生倍频信号。 从倍频信号产生同相本地振荡器信号和正交本地振荡器信号,使得同相本地振荡器和正交本地振荡器信号彼此不同相。 此外,检测同相本地振荡器信号和正交本地振荡器信号之间的相位关系,并且基于同相本地振荡器信号和正交本地振荡器信号之间的相位关系来生成反馈信号。

    Method and apparatus for self-testing a digital-to-analog converter (DAC) in an integrated circuit
    9.
    发明授权
    Method and apparatus for self-testing a digital-to-analog converter (DAC) in an integrated circuit 有权
    用于在集成电路中自我测试数模转换器(DAC)的方法和装置

    公开(公告)号:US08223048B2

    公开(公告)日:2012-07-17

    申请号:US12912446

    申请日:2010-10-26

    IPC分类号: H03M1/10

    CPC分类号: H03M1/109 H03M1/66

    摘要: An on-chip self testing digital-to-analog converter (DAC) is provided. The functionality of the DAC is measured using a combination of integral non-linearity (INL) and differential non-linearity (DNL). Parts may pass or be rejected based on the testing. When a DAC passes the testing, the process continues to the next DAC or quits if all the DACs have been tested.

    摘要翻译: 提供片上自检数模转换器(DAC)。 使用积分非线性(INL)和差分非线性(DNL)的组合来测量DAC的功能。 部件可能会根据测试通过或被拒绝。 当DAC通过测试时,如果所有的DAC都经过测试,该过程将继续下一个DAC或退出。

    METHOD AND APPARATUS FOR SELF-TESTING A DIGITAL-TO-ANALOG CONVERTER (DAC) IN AN INTEGRATED CIRCUIT
    10.
    发明申请
    METHOD AND APPARATUS FOR SELF-TESTING A DIGITAL-TO-ANALOG CONVERTER (DAC) IN AN INTEGRATED CIRCUIT 有权
    用于在集成电路中自动测试数字到模拟转换器(DAC)的方法和装置

    公开(公告)号:US20120098687A1

    公开(公告)日:2012-04-26

    申请号:US12912446

    申请日:2010-10-26

    IPC分类号: H03M1/10 H03M1/66

    CPC分类号: H03M1/109 H03M1/66

    摘要: An on-chip self testing digital-to-analog converter (DAC) is provided. The functionality of the DAC is measured using a combination of integral non-linearity (INL) and differential non-linearity (DNL). Parts may pass or be rejected based on the testing. When a DAC passes the testing, the process continues to the next DAC or quits if all the DACs have been tested.

    摘要翻译: 提供片上自检数模转换器(DAC)。 使用积分非线性(INL)和差分非线性(DNL)的组合来测量DAC的功能。 部件可能会根据测试通过或被拒绝。 当DAC通过测试时,如果所有的DAC都经过测试,该过程将继续下一个DAC或退出。