摘要:
A feedback loop with an adjustable closed loop frequency response. The feedback loop contains adjustable pole (212, 213) and adjustable zero elements (220,221) for changing the pole and/or zero locations in the feedback loop's loop frequency response thereby changing the closed loop frequency response of the feedback loop. In one embodiment, the feedback loop is a Cartesian feedback loop suitable for use in a radio transmitter.
摘要:
A transmitter is provided with a local oscillator (LO) processing unit to maintain stability in the transmitter's feedback loop. The LO processing unit includes at least one delay locked loop (DLL) and a programmable divider to generate phase shifted LO signals for adjusting a loop phase of the feedback loop in the transmitter. The generated phase shifted LO signals are of both a coarse and fine phase shifted nature. The adjustability and control of the coarse and fine phase shifting of the LO signals maintains linearity in the transmitter feedback loop.
摘要:
A transmitter is provided with a local oscillator (LO) processing unit to maintain stability in the transmitter's feedback loop. The LO processing unit includes at least one delay locked loop (DLL) and a programmable divider to generate phase shifted LO signals for adjusting a loop phase of the feedback loop in the transmitter. The generated phase shifted LO signals are of both a coarse and fine phase shifted nature. The adjustability and control of the coarse and fine phase shifting of the LO signals maintains linearity in the transmitter feedback loop.
摘要:
An apparatus and method produce a plurality of output signals (917-921) with fixed phase relationships therebetween. The apparatus (900) includes a first signal generator (901), a second signal generator (903), and a signal processor (907). The first signal generator produces a first input signal (911) at a first frequency. The second signal generator produces a second input signal (915) at a second frequency, wherein the second frequency is an integer multiple of the first frequency. The signal processor receives the first and second input signals and produces a plurality of output signals (917-921) having fixed phase relationships therebetween at the first frequency, wherein the fixed phase relationships are based on the integer multiple and wherein each of the output signals has a single, determinate phase relative to the phase of the first input signal.
摘要:
An apparatus and method produce a plurality of output signals (917-921) with fixed phase relationships therebetween. The apparatus (900) includes a first signal generator (901), a second signal generator (903), and a signal processor (907). The first signal generator produces a first input signal (911) at a first frequency. The second signal generator produces a second input signal (915) at a second frequency, wherein the second frequency is an integer multiple of the first frequency. The signal processor receives the first and second input signals and produces a plurality of output signals (917-921) having fixed phase relationships therebetween at the first frequency, wherein the fixed phase relationships are based on the integer multiple and wherein each of the output signals has a single, determinate phase relative to the phase of the first input signal.
摘要:
A linear amplifier (103) has a negative feedback loop that has a closed loop gain and a forward path gain. The negative feedback loop is closed, such that quick changes in the closed loop gain are prevented, thereby reducing splatter. When the negative feedback loop is opened, quick changes in the closed loop gain are also prevented, thereby reducing splatter.
摘要:
A synthesizer architecture, responsive to a low noise reference signal from a discrete oscillator, provides a continuous periodic output with a period that is a fractional multiple of the low noise reference signal. One exemplary embodiment includes a phase detector providing a control signal to a selected one of a plurality of integrated voltage controlled oscillators (VCO), wherein the phase detector is a sub-harmonic continuous time sampling phase detector. Another exemplary embodiment includes a continuous fractional divider input to the phase detector in response to an output of the selected VCO. Yet another exemplary embodiment comprises an injection locked ring oscillator responsive to the low noise narrow band variable reference signal with a fractional output period.
摘要:
Low noise phase quadrature signals are generated after receiving a clock signal and adjusting the clock signal in response to a feedback signal to generate a phase adjusted clock signal. The clock signal and the phase adjusted clock signal are exclusive-ored to generate a frequency doubled signal. An in-phase local oscillator signal and a quadrature local oscillator signal are generated from the frequency doubled signal such that the in-phase local oscillator and the quadrature local oscillator signal are out-of-phase with each other. In addition, a phase relationship between the in-phase local oscillator signal and the quadrature local oscillator signal are detected, and the feedback signal is generated based upon the phase relationship between the in-phase local oscillator signal and the quadrature local oscillator signal.
摘要:
An on-chip self testing digital-to-analog converter (DAC) is provided. The functionality of the DAC is measured using a combination of integral non-linearity (INL) and differential non-linearity (DNL). Parts may pass or be rejected based on the testing. When a DAC passes the testing, the process continues to the next DAC or quits if all the DACs have been tested.
摘要:
An on-chip self testing digital-to-analog converter (DAC) is provided. The functionality of the DAC is measured using a combination of integral non-linearity (INL) and differential non-linearity (DNL). Parts may pass or be rejected based on the testing. When a DAC passes the testing, the process continues to the next DAC or quits if all the DACs have been tested.