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公开(公告)号：US5079608A
公开(公告)日：1992-01-07
申请号：US609685
申请日：1990-11-06
CPC分类号： H03K17/0822 , H01L27/0251 , H01L29/7802 , H01L29/0696
摘要： A power MOS transistor, including source, drain, and gate electrodes, comprises a substrate of a semiconductor material of one conductivity type having first and second opposed surfaces; a drain region extending through the substrate between the surfaces; a plurality of spaced body regions of the opposite conductivity type extending into the substrate from the first surface; and a source region of the one conductivity type extending into the substrate from the first surface within each of the body regions, the interface of each of the source regions with its respective body region at the first surface being spaced from the interface of its respective body region and the drain region at the first surface to form a channel region therebetween. A gate electrode overlies and is insulated from the first surface and extends across the channel regions. A conductive electrode extends over and is insulated from the gate electrode, and contacts at least a portion of the source regions. A current limiting circuit is coupled between the conductive electrode and the gate electrode and a voltage limiting circuit is coupled between the drain electrode and the gate electrode.
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2.发明授权Power FET with gate segments covering drain regions disposed in a hexagonal pattern 失效功率FET，其栅极段覆盖以六边形图案设置的漏极区域
公开(公告)号：US5323036A
公开(公告)日：1994-06-21
申请号：US822732
申请日：1992-01-21
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/739 , H01L27/10 , H01L29/78
CPC分类号： H01L29/0696 , H01L29/1095 , H01L29/7395 , H01L29/4238
摘要： In a power FET composed of a substrate having upper and lower surfaces, the FET providing a current flow path between the upper and lower surfaces, and the FET having a plurality of drain regions extending to the substrate upper surface and an insulated gate electrode disposed on the upper surface, the improvement wherein said drain regions are disposed in a hexagonal lattice pattern, and said gate electrode comprises: a plurality of gate segments each covering a respective drain region; and a plurality of connecting segments each connecting together three of said gate segments.
摘要翻译： 在由具有上表面和下表面的衬底构成的功率FET中，FET在上表面和下表面之间提供电流流动路径，并且具有延伸到衬底上表面的多个漏区的FET和设置在衬底上的绝缘栅电极 上表面，其中所述漏极区域以六边形格子图案设置，并且所述栅极电极包括：多个栅极段，每个栅极段覆盖相应的漏极区域; 以及多个连接段，每个连接段将三个所述栅极段连接在一起。
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公开(公告)号：US5218220A
公开(公告)日：1993-06-08
申请号：US789901
申请日：1991-11-12
IPC分类号： H01L21/336 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/1095 , H01L29/42368
摘要： In a power FET composed of a substrate having upper and lower surfaces and having a semiconductor body of a first conductivity type, the body providing a current flow path between the upper and lower surfaces and having at least one body region which extends to said upper surface; and at least one base region extending into the substrate from the upper surface, the base region being of a second conductivity type opposite to the first conductivity type and having an upper portion located adjacent the upper surface of the substrate and a lower portion separated from the upper surface of the substrate by the upper portion, the upper portion defining a channel which is disposed in the current flow path adjacent the upper surface of the substrate, and the FET further having an insulated gate disposed at the upper surface above the body region, an impurity layer region extends into the channel from the upper surface of the substrate for giving the channel a lower impurity density than the lower portion of the base region.
摘要翻译： 在由具有上表面和下表面并且具有第一导电类型的半导体本体的基板组成的功率FET中，主体在上表面和下表面之间提供电流流动通道，并且具有延伸到所述上表面的至少一个主体区域 ; 以及从上表面延伸到基板中的至少一个基极区域，所述基极区域具有与第一导电类型相反的第二导电类型，并且具有邻近基板上表面的上部分， 所述上部设置在与所述基板的上表面相邻的所述电流流路中的通道，所述FET还具有设置在所述主体区域上方的上表面的绝缘栅， 杂质层区域从衬底的上表面延伸到沟道中，以使沟道的杂质密度低于基区的下部。
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4.发明授权Power VDMOSFET with schottky on lightly doped drain of lateral driver FET 失效具有肖特基功率的VDMOSFET在侧向驱动器FET的轻型漏极漏极上
公开(公告)号：US5164802A
公开(公告)日：1992-11-17
申请号：US672243
申请日：1991-03-20
申请人： Frederick P. Jones , Joseph A. Yedinak , John M. S. Neilson , Robert S. Wrathall , Jeffrey G. Mansmann , Claire E. Jackoski
发明人： Frederick P. Jones , Joseph A. Yedinak , John M. S. Neilson , Robert S. Wrathall , Jeffrey G. Mansmann , Claire E. Jackoski
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L29/7803 , H01L29/7806 , H01L29/7839
摘要： A monolithic semiconductor device comprises a VDMOS transistor having first and second main electrodes and a control electrode, and a lateral MOSFET having first and second main electrodes and a control electrode, wherein one of the first and second electrodes of the lateral MOSFET has a lower doping concentration than that of the first and second main electrodes of the VDMOS transistor for forming a Schottky barrier diode.
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公开(公告)号：US5399892A
公开(公告)日：1995-03-21
申请号：US158444
申请日：1993-11-29
IPC分类号： H01L29/06 , H01L29/739 , H01L29/78 , H01L29/10
CPC分类号： H01L29/0696 , H01L29/7802 , Y10S148/126
摘要： A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.
摘要翻译： 用于MOS门控半导体器件的晶片的图案包括从源极接触区域延伸到另一个源极接触区域的多个带，每个带子在两个沟道区域之间具有单个源极区域，以便增加器件的载流 相对于现有技术的每单位面积的能力。 该图案相对于源接触区域的面积增加了有效载流区域（器件的通道和颈部区域）的尺寸。 源极接触区可以是离散的或线性的，并且带可以从其垂直地或以其它角度延伸。
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6.发明授权Method of forming MOS-gated semiconductor devices having mesh geometry pattern 失效形成具有网格几何图案的MOS门控半导体器件的方法
公开(公告)号：US5468668A
公开(公告)日：1995-11-21
申请号：US368612
申请日：1995-01-04
IPC分类号： H01L29/06 , H01L29/739 , H01L29/78 , H01L21/77
CPC分类号： H01L29/0696 , H01L29/7802 , Y10S148/126
摘要： A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.
摘要翻译： 用于MOS门控半导体器件的晶片的图案包括从源极接触区域延伸到另一个源极接触区域的多个带，每个带子在两个沟道区域之间具有单个源极区域，以便增加器件的载流 相对于现有技术的每单位面积的能力。 该图案相对于源接触区域的面积增加了有效载流区域（器件的通道和颈部区域）的尺寸。 源极接触区可以是离散的或线性的，并且带可以从其垂直地或以其它角度延伸。
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