公开(公告)号：US5323036A

公开(公告)日：1994-06-21

申请号：US822732

申请日：1992-01-21

申请人： John M. S. Neilson ,  Frederick P. Jones ,  Joseph A. Yedinak ,  Christopher L. Rexer

发明人： John M. S. Neilson ,  Frederick P. Jones ,  Joseph A. Yedinak ,  Christopher L. Rexer

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L27/10 ,  H01L29/78

CPC分类号： H01L29/0696 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/4238

摘要： In a power FET composed of a substrate having upper and lower surfaces, the FET providing a current flow path between the upper and lower surfaces, and the FET having a plurality of drain regions extending to the substrate upper surface and an insulated gate electrode disposed on the upper surface, the improvement wherein said drain regions are disposed in a hexagonal lattice pattern, and said gate electrode comprises: a plurality of gate segments each covering a respective drain region; and a plurality of connecting segments each connecting together three of said gate segments.

摘要翻译： 在由具有上表面和下表面的衬底构成的功率FET中，FET在上表面和下表面之间提供电流流动路径，并且具有延伸到衬底上表面的多个漏区的FET和设置在衬底上的绝缘栅电极 上表面，其中所述漏极区域以六边形格子图案设置，并且所述栅极电极包括：多个栅极段，每个栅极段覆盖相应的漏极区域; 以及多个连接段，每个连接段将三个所述栅极段连接在一起。

公开(公告)号：US5218220A

公开(公告)日：1993-06-08

申请号：US789901

申请日：1991-11-12

申请人： John M. S. Neilson ,  Frederick P. Jones ,  Joseph A. Yedinak

发明人： John M. S. Neilson ,  Frederick P. Jones ,  Joseph A. Yedinak

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42368

摘要： In a power FET composed of a substrate having upper and lower surfaces and having a semiconductor body of a first conductivity type, the body providing a current flow path between the upper and lower surfaces and having at least one body region which extends to said upper surface; and at least one base region extending into the substrate from the upper surface, the base region being of a second conductivity type opposite to the first conductivity type and having an upper portion located adjacent the upper surface of the substrate and a lower portion separated from the upper surface of the substrate by the upper portion, the upper portion defining a channel which is disposed in the current flow path adjacent the upper surface of the substrate, and the FET further having an insulated gate disposed at the upper surface above the body region, an impurity layer region extends into the channel from the upper surface of the substrate for giving the channel a lower impurity density than the lower portion of the base region.

摘要翻译： 在由具有上表面和下表面并且具有第一导电类型的半导体本体的基板组成的功率FET中，主体在上表面和下表面之间提供电流流动通道，并且具有延伸到所述上表面的至少一个主体区域 ; 以及从上表面延伸到基板中的至少一个基极区域，所述基极区域具有与第一导电类型相反的第二导电类型，并且具有邻近基板上表面的上部分， 所述上部设置在与所述基板的上表面相邻的所述电流流路中的通道，所述FET还具有设置在所述主体区域上方的上表面的绝缘栅， 杂质层区域从衬底的上表面延伸到沟道中，以使沟道的杂质密度低于基区的下部。

公开(公告)号：US5164802A

公开(公告)日：1992-11-17

申请号：US672243

申请日：1991-03-20

申请人： Frederick P. Jones ,  Joseph A. Yedinak ,  John M. S. Neilson ,  Robert S. Wrathall ,  Jeffrey G. Mansmann ,  Claire E. Jackoski

发明人： Frederick P. Jones ,  Joseph A. Yedinak ,  John M. S. Neilson ,  Robert S. Wrathall ,  Jeffrey G. Mansmann ,  Claire E. Jackoski

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/7803 ,  H01L29/7806 ,  H01L29/7839

摘要： A monolithic semiconductor device comprises a VDMOS transistor having first and second main electrodes and a control electrode, and a lateral MOSFET having first and second main electrodes and a control electrode, wherein one of the first and second electrodes of the lateral MOSFET has a lower doping concentration than that of the first and second main electrodes of the VDMOS transistor for forming a Schottky barrier diode.

公开(公告)号：US5079608A

公开(公告)日：1992-01-07

申请号：US609685

申请日：1990-11-06

申请人： Paul J. Wodarczyk ,  Frederick P. Jones ,  John M. S. Neilson ,  Joseph A. Yedinak

发明人： Paul J. Wodarczyk ,  Frederick P. Jones ,  John M. S. Neilson ,  Joseph A. Yedinak

IPC分类号： H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/06 ,  H01L29/78

CPC分类号： H03K17/0822 ,  H01L27/0251 ,  H01L29/7802 ,  H01L29/0696

摘要： A power MOS transistor, including source, drain, and gate electrodes, comprises a substrate of a semiconductor material of one conductivity type having first and second opposed surfaces; a drain region extending through the substrate between the surfaces; a plurality of spaced body regions of the opposite conductivity type extending into the substrate from the first surface; and a source region of the one conductivity type extending into the substrate from the first surface within each of the body regions, the interface of each of the source regions with its respective body region at the first surface being spaced from the interface of its respective body region and the drain region at the first surface to form a channel region therebetween. A gate electrode overlies and is insulated from the first surface and extends across the channel regions. A conductive electrode extends over and is insulated from the gate electrode, and contacts at least a portion of the source regions. A current limiting circuit is coupled between the conductive electrode and the gate electrode and a voltage limiting circuit is coupled between the drain electrode and the gate electrode.

公开(公告)号：US08836028B2

公开(公告)日：2014-09-16

申请号：US13095690

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Dwayne S. Reichl ,  Harold Heidenreich

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Dwayne S. Reichl ,  Harold Heidenreich

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/0878 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.

摘要翻译： 在一般方面，功率器件可以包括设置在衬底上的至少一个N型外延层和在所述至少一个N型外延层中限定交替的P-N柱的多个N柱和P柱。 功率器件还可以包括有源区和端接区，其中终端区围绕有源区。 交替的P-N柱可以设置在有源区域和终止区域中，其中终止区域可以包括预定数量的浮动P柱。

公开(公告)号：US08564024B2

公开(公告)日：2013-10-22

申请号：US12421448

申请日：2009-04-09

申请人： Joseph A. Yedinak ,  Ashok Challa ,  Daniel M. Kinzer ,  Dean E. Probst

发明人： Joseph A. Yedinak ,  Ashok Challa ,  Daniel M. Kinzer ,  Dean E. Probst

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7827 ,  H01L29/872 ,  H01L29/8725

摘要： Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

公开(公告)号：US08563377B2

公开(公告)日：2013-10-22

申请号：US13443986

申请日：2012-04-11

申请人： Joseph A. Yedinak ,  Daniel Calafut ,  Dean E. Probst

发明人： Joseph A. Yedinak ,  Daniel Calafut ,  Dean E. Probst

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7827 ,  H01L29/872 ,  H01L29/8725

摘要： Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

公开(公告)号：US20120273916A1

公开(公告)日：2012-11-01

申请号：US13095652

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

发明人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

IPC分类号： H01L29/872

CPC分类号： H01L29/0634 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

公开(公告)号：US20120193748A1

公开(公告)日：2012-08-02

申请号：US13443986

申请日：2012-04-11

申请人： Joseph A. Yedinak ,  Daniel Calafut ,  Dean E. Probst

发明人： Joseph A. Yedinak ,  Daniel Calafut ,  Dean E. Probst

IPC分类号： H01L29/06

CPC分类号： H01L29/7813 ,  H01L29/0611 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7827 ,  H01L29/872 ,  H01L29/8725

摘要： Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

摘要翻译： 公开了具有提供增加的击穿电压和其它益处的特征的功率半导体器件。

公开(公告)号：US08043913B2

公开(公告)日：2011-10-25

申请号：US13075091

申请日：2011-03-29

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Boguslaw Kocon ,  Steven P. Sapp ,  Dean E. Probst ,  Nathan L. Kraft ,  Thomas E. Grebs ,  Rodney S. Ridley ,  Gary M. Dolny ,  Bruce D. Marchant ,  Joseph A. Yedinak

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Boguslaw Kocon ,  Steven P. Sapp ,  Dean E. Probst ,  Nathan L. Kraft ,  Thomas E. Grebs ,  Rodney S. Ridley ,  Gary M. Dolny ,  Bruce D. Marchant ,  Joseph A. Yedinak

IPC分类号： H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.

摘要翻译： 形成场效应晶体管的方法包括：在半导体区域中形成沟槽; 在沟槽中形成屏蔽电极; 执行第一导电类型的杂质的成角度的侧壁注入，以形成与沟槽相邻的沟道增强区域; 在半导体区域中形成第二导电类型的体区; 并且在所述体区域中形成所述第一导电类型的源极区域，所述源极区域和所述体区域与所述半导体区域之间的界面在所述体区域中形成沟道区域，所述沟道区域沿着所述沟槽侧壁延伸。 沟道增强区域部分地延伸到沟道区的下部，从而减小沟道区的电阻。