公开(公告)号：US20070061547A1

公开(公告)日：2007-03-15

申请号：US11222577

申请日：2005-09-09

申请人： Paul Jordan ,  Manish Shah ,  Gregory Grohoski

发明人： Paul Jordan ,  Manish Shah ,  Gregory Grohoski

IPC分类号： G06F12/00

CPC分类号： G06F12/1054 ,  G06F12/1027 ,  G06F12/109 ,  G06F2212/656 ,  G06F2212/682 ,  G06F2212/683

摘要： In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of strands. Each strand comprises hardware to support a different thread of a plurality of concurrently activateable threads in the processor. The strands share the TLB, and the control unit is configured to delay a demap operation issued from one of the estrands responsive to the pending update, if any.

摘要翻译： 在一个实施例中，处理器包括至少一个翻译后备缓冲器（TLB）和耦合到该TLB的控制单元。 控制单元被配置为跟踪针对多个线段中的至少一个的至少一个对TLB的更新是否待决。 每条链包括用于支持处理器中多个可同时激活的线程的不同线程的硬件。 链路共享TLB，并且控制单元被配置为响应于待决更新（如果有的话）延迟从一个estrand发出的解映射操作。

公开(公告)号：US20070061548A1

公开(公告)日：2007-03-15

申请号：US11222614

申请日：2005-09-09

申请人： Paul Jordan ,  Manish Shah ,  Gregory Grohoski

发明人： Paul Jordan ,  Manish Shah ,  Gregory Grohoski

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F2212/682 ,  G06F2212/683

摘要： In one embodiment, a processor comprises a plurality of processor cores and an interconnect to which the plurality of processor cores are coupled. Each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB). A first processor core is configured to broadcast a demap command on the interconnect responsive to executing a demap operation. The demap command identifies one or more translations to be invalidated in the TLBs, and remaining processor cores are configured to invalidate the translations in the respective TLBs. The remaining processor cores transmit a response to the first processor core, and the first processor core is configured to delay continued processing subsequent to the demap operation until the responses are received from each of the remaining processor cores.

摘要翻译： 在一个实施例中，处理器包括多个处理器核和多个处理器核耦合到的互连。 多个处理器核心中的每一个包括至少一个平移后备缓冲器（TLB）。 第一处理器核心被配置为响应于执行解映射操作而在互连上广播解映射命令。 解映射命令标识在TLB中将被无效的一个或多个翻译，并且剩余的处理器核被配置为使相应TLB中的翻译无效。 剩余的处理器核心向第一处理器核心发送响应，并且第一处理器核心被配置为延迟解映射操作之后的持续处理，直到从每个其余处理器核心接收到响应。

公开(公告)号：US11783206B1

公开(公告)日：2023-10-10

申请号：US16102004

申请日：2018-08-13

申请人： Anoop Makwana ,  Manish Shah ,  Goutham Kallepalli ,  Aminish Sharma ,  Shashi Roshan ,  Venkata Giri Sirigiri

发明人： Anoop Makwana ,  Manish Shah ,  Goutham Kallepalli ,  Aminish Sharma ,  Shashi Roshan ,  Venkata Giri Sirigiri

IPC分类号： G06N5/04 ,  G06N20/00 ,  G06Q10/04

CPC分类号： G06N5/04 ,  G06N20/00 ,  G06Q10/04

摘要： A method for making binary predictions for a subject involves obtaining historical data for multiple subjects, the historical data including, for each subject, a feature set and a binary outcome, generating training data from the historical data, and training a predictive model using the training data to predict the outcomes based on the feature sets. The method further includes obtaining historical data including a feature set for a subject under consideration, and predicting a binary outcome for the subject under consideration, based on the feature set associated with the subject under consideration.

公开(公告)号：US20190216472A1

公开(公告)日：2019-07-18

申请号：US16326347

申请日：2017-07-19

申请人： Manish Shah

发明人： Manish Shah

IPC分类号： A61B17/15 ,  A61F2/38 ,  A61F2/46

CPC分类号： A61B17/155 ,  A61F2/3859 ,  A61F2/461 ,  A61F2002/3055

摘要： The present jig for guiding placement of femoral component of the implant in a knee replacement surgery (J) is a pre-assembled Jig (J) that ensures precision fit femoral implant for knee replacement based on difference of cuts in millimeters instead of the usual angle measurement in degrees. It avoids intrusion of the intramedullary canal substantially decreasing the risks of embolism. It enables the surgeon to use precise values of depth of cuts obtained from a system for obtaining optimum fit implant as described in patent application number 3896/MUM2015. This enables the surgeon to control precisely the placement of the implant in terms of flexion or extension, varus or valgus, internal or external rotation. It also enables precise placement of the four-in-one cutting block simultaneously with the distal femur cut; ensuring precise placement of knee femoral component of the knee implant. This reduces efforts and time taken during surgery.

公开(公告)号：US08195919B1

公开(公告)日：2012-06-05

申请号：US11927177

申请日：2007-10-29

申请人： Christopher H. Olson ,  Robert T. Golla ,  Manish Shah ,  Jeffrey S. Brooks

发明人： Christopher H. Olson ,  Robert T. Golla ,  Manish Shah ,  Jeffrey S. Brooks

IPC分类号： G06F13/00

CPC分类号： G06F12/0842 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3824 ,  G06F12/0855

摘要： Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented memory. During that cycle, the processor determines whether a memory segment base is zero. If the segment base is zero, the processor can access a memory location at the effective address without adding the segment base. If the segment base is not zero, such as when executing legacy code, the processor consumes another cycle to add the segment base to the effective address. Similarly, the processor consumes another cycle if the effective address or the linear address is misaligned. An integer execution unit that performs the three-operand add using a carry-save adder coupled to a carry look-ahead adder. If the segment base is not zero, the effective address is fed back through the integer execution unit to add the segment base.

摘要翻译： 在可以访问分段存储器和非分段存储器的多线程处理器的单个执行周期中确定具有三操作数添加操作的存储器的有效地址。 在该周期期间，处理器确定存储器段基数是否为零。 如果分段基数为零，则处理器可以在有效地址的情况下访问存储器位置，而不添加分段基。 如果段基数不为零，例如执行遗留代码时，处理器消耗另一个周期，将段基数添加到有效地址。 类似地，如果有效地址或线性地址不对齐，则处理器消耗另一个周期。 整数执行单元，其使用耦合到进位先行加法器的进位保存加法器来执行三运算加法。 如果段基数不为零，则通过整数执行单元反馈有效地址以添加段基。

公开(公告)号：US08099586B2

公开(公告)日：2012-01-17

申请号：US12346349

申请日：2008-12-30

申请人： Yuan C. Chou ,  Robert T. Golla ,  Mark A. Luttrell ,  Paul J. Jordan ,  Manish Shah

发明人： Yuan C. Chou ,  Robert T. Golla ,  Mark A. Luttrell ,  Paul J. Jordan ,  Manish Shah

IPC分类号： G06F9/00

CPC分类号： G06F9/3844 ,  G06F9/3863

摘要： A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.

摘要翻译： 减少分支误判处罚的系统和方法。 响应于检测到错误的分支指令，微处理器内的电路在退出分支指令之前识别预定的条件。 在识别该条件之后，在分支指令退出之前将整个对应的流水线冲洗，并且在冲洗流水线之前在管道中的最早的指令的对应地址开始指令提取。 在管道冲洗之前存储正确的结果。 为了将错误预测的分支与其他指令区分开，识别信息可以与正确的结果一起存储。 满足预定条件的一个示例是响应于定时器达到预定阈值，其中定时器响应于错误预测的分支检测而开始递增，并且在退出预测分支时重置。

公开(公告)号：US07822850B1

公开(公告)日：2010-10-26

申请号：US12013146

申请日：2008-01-11

申请人： Yevgeniy Brikman ,  Manish Shah ,  Paul Antinori ,  Harun Gadatia ,  Vipin Palawat

发明人： Yevgeniy Brikman ,  Manish Shah ,  Paul Antinori ,  Harun Gadatia ,  Vipin Palawat

IPC分类号： G06F15/173

CPC分类号： G06F17/30914 ,  Y10S707/99943

摘要： Described in an example embodiment herein is a method for extracting values from a plurality of data fields from a log file using a grammar file. The plurality of data fields and a procedure for extracting values from the plurality of data fields are defined in the grammar file. Extracted values are analyzed and graphically represented.

摘要翻译： 在这里的示例性实施例中描述的是一种从使用语法文件的日志文件中提取多个数据字段的值的方法。 多个数据字段和用于从多个数据字段提取值的过程在语法文件中被定义。 提取的值被分析和图形化。

公开(公告)号：US20070072193A1

公开(公告)日：2007-03-29

申请号：US11237395

申请日：2005-09-27

申请人： Manish Shah

发明人： Manish Shah

IPC分类号： C12Q1/68 ,  G01N33/53 ,  C12M3/00

CPC分类号： B01J19/0046 ,  B01J2219/00378 ,  B01J2219/00441 ,  B01J2219/00527 ,  B01J2219/00605 ,  B01J2219/00612 ,  B01J2219/00626 ,  B01J2219/00637 ,  B01J2219/00659 ,  B01J2219/00722 ,  B01J2219/00725

摘要： Methods and compositions for producing a solid support having a ligand immobilized on a surface thereof, e.g. a ligand array, are provided. Aspects of the methods include: providing a solid support having a bounded feature location on a surface thereof, where the bounded feature location includes a region of the surface at least partially bounded by an electromagnetic radiation modified boundary; and producing a ligand in the feature location. Also provided are systems for practicing the subject methods, as well as devices produced by the methods and methods of using such devices.

摘要翻译： 用于生产具有固定在其表面上的配体的固体支持物的方法和组合物，例如， 配体阵列。 方法的方面包括：提供具有在其表面上的有界特征位置的固体支撑体，其中有界特征位置包括至少部分地由电磁辐射修饰边界界限的表面区域; 并在特征位置产生配体。 还提供了用于实践主题方法的系统，以及通过使用这些装置的方法和方法产生的装置。

公开(公告)号：US20130232106A1

公开(公告)日：2013-09-05

申请号：US13410163

申请日：2012-03-01

申请人： Manish Shah ,  Sachindatta Dhamane

发明人： Manish Shah ,  Sachindatta Dhamane

IPC分类号： G06F17/30

CPC分类号： G06F16/23

摘要： A computer-implemented method for updating multiple data records in a database in a single transaction. The method includes searching a data model associated with the data records in the database for fields related to an objective. Once complete, a user will enter new objective values associated with the objective. The processor then performs a business rule validation of the fields found during the searching step with the new objective values entered. The report is then displayed to a user on a display. The user reviews the report and may approve the new objective values. If approved, the finalized objective values are applied to the database.

摘要翻译： 一种用于在单个事务中更新数据库中的多个数据记录的计算机实现的方法。 该方法包括搜索与数据库中的数据记录相关联的数据模型，用于与目标相关的字段。 一旦完成，用户将输入与目标相关联的新客观值。 然后处理器对搜索步骤中找到的字段执行业务规则验证，并输入新的客观值。 然后，报告将显示给用户。 用户审查报告，并可能批准新的客观价值观。 如果批准，最终的目标值将应用于数据库。

公开(公告)号：US08195921B2

公开(公告)日：2012-06-05

申请号：US12170144

申请日：2008-07-09

申请人： Robert Golla ,  Manish Shah

发明人： Robert Golla ,  Manish Shah

IPC分类号： G06F15/00

CPC分类号： G06F9/3017 ,  G06F9/26 ,  G06F9/30145 ,  G06F9/3851

摘要： A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads is disclosed. The microprocessor may comprise a first array comprising a first plurality of microcode operations associated with an instruction from within the plurality of instructions, the first array capable of delivering a first predetermined number of microcode operations from the first plurality of microcode operations. The microprocessor may further comprise a second array comprising a second plurality of microcode operations, the second array capable of providing one or more of the second plurality of microcode operations in the event that the instruction decodes into more than the first predetermined number of microcode operations. The microprocessor may further comprise an arbiter coupled between the first and second arrays, where the arbiter may determine which thread from the plurality of threads accesses the second array.

摘要翻译： 公开了能够解码与多个线程相关联的多个指令的微处理器。 微处理器可以包括第一阵列，其包括与来自多个指令内的指令相关联的第一多个微代码操作，第一阵列能够从第一多个微代码操作传送第一预定数量的微代码操作。 微处理器还可以包括包括第二多个微代码操作的第二阵列，所述第二阵列能够在所述指令解码成多于所述第一预定数量的微代码操作的情况下能够提供所述第二多个微代码操作中的一个或多个。 微处理器还可以包括耦合在第一和第二阵列之间的仲裁器，其中仲裁器可以确定来自多个线程的线程访问第二阵列。