公开(公告)号：US06816990B2

公开(公告)日：2004-11-09

申请号：US10058485

申请日：2002-01-28

申请人： Peilin Song ,  Timothy J. Koprowski ,  Ulrich Baur ,  Franco Motika

发明人： Peilin Song ,  Timothy J. Koprowski ,  Ulrich Baur ,  Franco Motika

IPC分类号： G01R3128

CPC分类号： G01R31/31721 ,  G01R31/31707 ,  G01R31/318307 ,  G01R31/318502 ,  G01R31/318522 ,  G01R31/3187

摘要： LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.

摘要翻译： LBIST和加权LBIST测试在测试对象的不同部分上同时进行。 这种新的测试方法和设计变化与传统的测试策略相比，测试覆盖率和测试时间都大大降低。 它可以应用于晶圆，芯片，MCM和系统测试级别。 最重要的是，它不需要新的支持工具。 当前的测试软件将与传统的测试策略一样工作。 在相同测试会话中调度LBIST和加权LBIST测试降低了整体功耗，因为加权LBIST测试比平面LBIST测试消耗的功率少得多。 在相同的测试会话中，如果使用加权LBIST测试逻辑的某些部分，而使用LBIST测试其他部分，则电路元件在任何给定时间消耗的功率降低。

公开(公告)号：US06662324B1

公开(公告)日：2003-12-09

申请号：US09642371

申请日：2000-08-21

申请人： Franco Motika ,  Richard F. Rizzolo ,  Peilin Song ,  William V. Huott ,  Ulrich Baur

发明人： Franco Motika ,  Richard F. Rizzolo ,  Peilin Song ,  William V. Huott ,  Ulrich Baur

IPC分类号： G01R3128

CPC分类号： G01R31/318525 ,  G01R31/31853 ,  G01R31/31858

摘要： The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function. In this design, the latch to be complemented does not require an additional input containing the complement value, but rather uses its current state as reference and switches to the opposite state. To accomplish this, a complement signal similar to a latch reset (i.e., reset-to-complement) can be used.

摘要翻译： 本发明能够在不改变另一个状态的情况下补充移位寄存器锁存器（SRL）中的主（L1）或从锁存器（L2）的状态。 当使用正常扫描链序列正确加载LSSD扫描链后，可以使用下一个系统时钟序列来启动扫描链中每个SRL所需的转换。 补充LSSD扫描链中锁存器状态的实际机制可以根据L1或L2锁存器中的哪一个进行补充而变化; 实际扫描链和Shift Register Latch（SRL）设计的细节; 和半导体芯片电路技术。 补充功能可以作为SRL设计的一个组成部分提供，对系统路径和性能影响最小。 一种替代的补充方法是使用自补充锁存功能。 在这种设计中，要补充的锁存器不需要包含补码值的附加输入，而是使用其当前状态作为参考，并切换到相反的状态。 为了实现这一点，可以使用类似于锁存器复位（即，复位到补码）的补码信号。

公开(公告)号：US06728914B2

公开(公告)日：2004-04-27

申请号：US09745603

申请日：2000-12-22

申请人： Kevin William McCauley ,  William Vincent Huott ,  Mary Prilotski Kusko ,  Peilin Song ,  Richard Frank Rizzolo ,  Ulrich Baur ,  Franco Motika

发明人： Kevin William McCauley ,  William Vincent Huott ,  Mary Prilotski Kusko ,  Peilin Song ,  Richard Frank Rizzolo ,  Ulrich Baur ,  Franco Motika

IPC分类号： G01R3128

CPC分类号： G01R31/318385 ,  G01R31/31858

摘要： For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated. When all the faults paths of the group falling below the threshold have been tested, a separate determined test generation program is activated. In the generated test, the fault is forced to propagate through the longest path above the threshold value.

摘要翻译： 对于逻辑电路中的每个逻辑门，确定包含门的所有路径，并且通过其每个输入或启动SRL和每个输出或捕获SRL之间的长度对路径进行分类。 路径被分配单个阈值，然后根据它们相对于阈值的路径长度分类被分成两组，每组中的所有路径被视为单个路径。 然后使用标准LBIST工具模拟伪随机LBIST图案。 当与逻辑门相关联的故障由长度高于阈值的路径的捕获​​SRL检测到时，故障被视为测试并从故障列表中标记出来。 当在低于阈值的任何路径中检测到故障时，它不会被标记，并且故障的测试继续进行，直到测试模式为低于阈值的组的所有路径。 当组件的所有故障路径都低于阈值时，已经测试了单独确定的测试生成程序。 在生成的测试中，故障被迫通过超过阈值的最长路径传播。

公开(公告)号：US06327685B1

公开(公告)日：2001-12-04

申请号：US09310444

申请日：1999-05-12

申请人： Timothy J. Koprowski ,  Franco Motika

发明人： Timothy J. Koprowski ,  Franco Motika

IPC分类号： G01R3128

CPC分类号： G01R31/3181

摘要： A BIST method that modifies the scan chain path and scan clocks to allow for distributed BIST test. In this distributed BIST concept, the Linear Feedback Shift Register (LFSR) and the Multiple Input Signature Register (MISR) are combined as an integral part of the scan chain, and each scan cycle is utilized as a test cycle.

摘要翻译： BIST方法修改扫描链路和扫描时钟以允许分布式BIST测试。 在这种分布式BIST概念中，线性反馈移位寄存器（LFSR）和多输入签名寄存器（MISR）被组合为扫描链的组成部分，并且每个扫描周期被用作测试周期。

公开(公告)号：US06968489B2

公开(公告)日：2005-11-22

申请号：US10055275

申请日：2002-01-23

申请人： Franco Motika ,  Timothy J. Koprowski

发明人： Franco Motika ,  Timothy J. Koprowski

IPC分类号： G01R31/3181 ,  G01R31/3185 ,  G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318385 ,  G01R31/31813 ,  G01R31/318547

摘要： Flat pseudo random test patterns are provided in combination with weighted pseudo random test patterns so that the weight applied to every latch in a LSSD shift register (SR) chain can be changed on every cycle. This enables integration of on-chip weighted pattern generation with either internal or external weight set selection. WRP patterns are generated by a tester either externally or internally to a device under test (DUT) and loaded via the shift register inputs (SRIs or WPIs) into the chip's shift register latches (SRLs). A test (or LSSD tester loop sequence) includes loading the SRLs in the SR chains with a WRP, pulsing the appropriate clocks, and unloading the responses captured in the SRLs into the multiple input signature register (MISR). Each test can then be applied multiple times for each weight set, with the weight-set assigning a weight factor or probability to each SRL.

摘要翻译： 平坦伪随机测试模式与加权伪随机测试模式相结合提供，以便可以在每个周期改变应用于LSSD移位寄存器（SR）链中的每个锁存器的权重。 这使得片内加权模式生成与内部或外部权重集合选择的集成。 WRP模式由测试仪在外部或内部生成到被测器件（DUT），并通过移位寄存器输入（SRI或WPI）加载到芯片的移位寄存器锁存器（SRL）中。 测试（或LSSD测试器循环序列）包括使用WRP加载SR链中的SRL，脉冲相应的时钟，并将在SRL中捕获的响应卸载到多输入签名寄存器（MISR）中。 然后可以对每个权重集合多次应用每个测试，权重集为每个SRL分配权重因子或概率。

公开(公告)号：US06442723B1

公开(公告)日：2002-08-27

申请号：US09310445

申请日：1999-05-12

申请人： Timothy J. Koprowski ,  Franco Motika ,  Phillip J. Nigh

发明人： Timothy J. Koprowski ,  Franco Motika ,  Phillip J. Nigh

IPC分类号： G01R313185

CPC分类号： G01R31/318371

摘要： LBIST resource parameters are used to control the data inputs for the signature generation process. These resource parameters include a LBIST pattern cycle counter, a channel input selected to input the MISR, and a channel load/unload shift counter. Properly setting one or more of these resource parameters to conditionally control those latch content values that get clocked into the MISR during the unload operation generates a three dimensional signature space.

摘要翻译： LBIST资源参数用于控制签名生成过程的数据输入。 这些资源参数包括LBIST模式周期计数器，选择输入MISR的通道输入和通道加载/卸载移位计数器。 适当地设置这些资源参数中的一个或多个以有条件地控制在卸载操作期间被计入MISR的锁存内容值产生三维签名空间。

公开(公告)号：US20050188290A1

公开(公告)日：2005-08-25

申请号：US10780878

申请日：2004-02-19

申请人： Franco Motika ,  Peilin Song

发明人： Franco Motika ,  Peilin Song

IPC分类号： G01R31/28 ,  G01R31/311 ,  G01R31/3185

CPC分类号： G01R31/318547 ,  G01R31/311

摘要： A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.

摘要翻译： 测试，诊断和监视电子电路的操作中的至少一个的方法（和结构）包括中断用于为电路的正常操作提供时钟的时钟信号，并且使用第二时钟信号重复循环 通过电路的预定操作周期。

公开(公告)号：US07089474B2

公开(公告)日：2006-08-08

申请号：US10789710

申请日：2004-02-27

申请人： Todd M. Burdine ,  Franco Motika ,  Peilin Song

发明人： Todd M. Burdine ,  Franco Motika ,  Peilin Song

IPC分类号： G06F11/00 ,  G06F17/50

CPC分类号： G06F11/261 ,  G01R31/31703 ,  G01R31/318371 ,  G06F11/263

摘要： A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorithmic test patterns for the one or more circuits in response to the first failing region and to a logic model of the integrated circuit. Expected results for the test patterns are determined. The method includes applying the test patterns to the first failing region on the integrated circuit resulting in actual results for the test patterns. The expected results to the actual results are compared. The method also transmits mismatches between the expected results and the actual results to a fault simulator. The method includes receiving a second failing region from the fault simulator, the second failing region created in response to the mismatches and the logic model, and the second failing region corresponding to a subset of the one or more circuits on the integrated circuit.

摘要翻译： 一种用于提供集成电路的交互式和迭代测试的方法，包括接收第一故障区域。 第一故障区域对应于集成电路上的一个或多个电路。 该方法响应于第一故障区域和集成电路的逻辑模型生成针对一个或多个电路的一组自适应算法测试模式。 确定测试模式的预期结果。 该方法包括将测试图案应用于集成电路上的第一故障区域，从而得到测试图案的实际结果。 对实际结果的预期结果进行比较。 该方法还将预期结果与实际结果之间的错配传输到故障模拟器。 该方法包括从故障模拟器接收第二故障区域，响应于不匹配和逻辑模型而创建的第二故障区域，以及对应于集成电路上的一个或多个电路的子集的第二故障区域。

公开(公告)号：US07480882B1

公开(公告)日：2009-01-20

申请号：US12049344

申请日：2008-03-16

申请人： Peilin Song ,  David Heidel ,  Franco Motika ,  Franco Stellari

发明人： Peilin Song ,  David Heidel ,  Franco Motika ,  Franco Stellari

IPC分类号： G06F17/50 ,  G06F19/00 ,  G06F11/27 ,  G01R31/3187 ,  G01R31/28

CPC分类号： G01R31/318536

摘要： This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.

摘要翻译： 该实施例取代了LBIST的使用以获得通过或不通过结果。 选择性签名功能用于通过在一个周期时间内抖动芯片来收集顶部故障路径。 这些路径可以片上或片外存储，供以后使用。 一旦芯片在现场运行一段时间，执行相同的过程来收集最上面的故障路径，并将其与存储的旧路径进行比较。 如果顶部路径的顺序发生变化，则表示（例如）有一个路径（不是最慢的路径）比其他路径慢，这可能是潜在的可靠性问题。 因此，在现场确定潜在的可靠性故障。

公开(公告)号：US07308626B2

公开(公告)日：2007-12-11

申请号：US10780878

申请日：2004-02-19

申请人： Franco Motika ,  Peilin Song

发明人： Franco Motika ,  Peilin Song

IPC分类号： G01R31/28

CPC分类号： G01R31/318547 ,  G01R31/311

摘要： A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.

摘要翻译： 测试，诊断和监视电子电路的操作中的至少一个的方法（和结构）包括中断用于为电路的正常操作提供时钟的时钟信号，并且使用第二时钟信号重复循环 通过电路的预定操作周期。