公开(公告)号：US20110257953A1

公开(公告)日：2011-10-20

申请号：US12762848

申请日：2010-04-19

申请人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

发明人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

摘要： A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

摘要翻译： 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：US08626474B2

公开(公告)日：2014-01-07

申请号：US12762848

申请日：2010-04-19

申请人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

发明人： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC分类号： G06F7/60 ,  G06G7/62 ,  G06F17/50

CPC分类号： G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

摘要： A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

摘要翻译： 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：US08504882B2

公开(公告)日：2013-08-06

申请号：US12884305

申请日：2010-09-17

申请人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

发明人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

IPC分类号： G06F11/00

CPC分类号： G06F11/267

摘要： An integrated circuit (“IC”) includes circuitry for use in testing a serial data signal. One such IC includes circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. One such IC also includes circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. Such an IC provides output signals indicative of results of its operations. One such IC operates in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

摘要翻译： 集成电路（“IC”）包括用于测试串行数据信号的电路。 一个这样的IC包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 一个这样的IC还包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 这样的IC提供指示其操作结果的输出信号。 一个这样的IC以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

公开(公告)号：US20120072785A1

公开(公告)日：2012-03-22

申请号：US12884923

申请日：2010-09-17

申请人： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

发明人： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

IPC分类号： G06F11/00

CPC分类号： H04L1/203 ,  G01R31/3171

摘要： An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

摘要翻译： 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

公开(公告)号：US20120072784A1

公开(公告)日：2012-03-22

申请号：US12884305

申请日：2010-09-17

申请人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Sriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

发明人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Sriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

IPC分类号： G06F11/00

CPC分类号： G06F11/267

摘要： An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

摘要翻译： 集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等功能，用于在抖动容限，噪声容限等方面测试信号和电路。

公开(公告)号：US09222972B1

公开(公告)日：2015-12-29

申请号：US12884747

申请日：2010-09-17

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Mingde Pan ,  Peng Li ,  Masashi Shimanouchi

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Mingde Pan ,  Peng Li ,  Masashi Shimanouchi

IPC分类号： G01R31/02 ,  G01R31/317

CPC分类号： G01R31/31709

摘要： An IC that includes a jitter generator, where the jitter generator is integral with the IC and generates non-intrinsic jitter, is provided. In one implementation, the non-intrinsic jitter is used to measure a characteristic of the IC. In one implementation, the non-intrinsic jitter is used to test jitter tolerance of the IC. In yet another implementation, the non-intrinsic jitter is used to test another IC coupled to the IC that includes the jitter generator.

摘要翻译： 提供了包括抖动发生器的IC，其中抖动发生器与IC集成并产生非固有抖动。 在一个实现中，非固有抖动用于测量IC的特性。 在一个实现中，非固有抖动用于测试IC的抖动容限。 在又一实现中，使用非固有抖动来测试耦合到包括抖动发生器的IC的另一IC。

公开(公告)号：US08750406B2

公开(公告)日：2014-06-10

申请号：US13363098

申请日：2012-01-31

申请人： Mingde Pan ,  Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Masashi Shimanouchi

发明人： Mingde Pan ,  Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Masashi Shimanouchi

IPC分类号： H04L25/34 ,  H04L25/49

CPC分类号： H04L25/4917 ,  H03D1/00 ,  H04L25/066 ,  H04L27/06

摘要： One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及用于多电平振幅信令的接收机电路，其包括用于每个符号周期的至少三个幅度电平。 接收器电路包括峰值检测器，参考电压发生器和比较器电路。 峰值检测器被设置为检测多电平幅度信号的峰值电压，并且参考电压发生器使用峰值电压来产生多个参考电压。 比较器电路使用多个参考电压来检测多电平幅度信号的幅度电平。 还公开了其它实施例和特征。

公开(公告)号：US08433958B2

公开(公告)日：2013-04-30

申请号：US12884923

申请日：2010-09-17

申请人： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

发明人： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

IPC分类号： G06F11/00

CPC分类号： H04L1/203 ,  G01R31/3171

摘要： An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

摘要翻译： 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

公开(公告)号：US08290750B1

公开(公告)日：2012-10-16

申请号：US13036437

申请日：2011-02-28

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

IPC分类号： H03F1/26

CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

公开(公告)号：US07860203B1

公开(公告)日：2010-12-28

申请号：US11725653

申请日：2007-03-19

申请人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

发明人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.

摘要翻译： 可编程逻辑器件集成电路（“PLD”）除了可编程逻辑电路之外还包括高速串行接口（“HSSI”）电路。 HSSI电路包括多个标称数据处理电路（通常包括时钟和数据恢复（“CDR”）电路）的通道，以及标称时钟管理单元（“CMU”）电路的至少一个通道（通常包括锁相环 （“PLL”）电路等）。 为了增加可以使用信道的灵活性，标称数据处理信道被配备为交替执行CMU类型功能，并且标称CMU信道被配备为备选地执行数据处理功能。