公开(公告)号：US20120005471A1

公开(公告)日：2012-01-05

申请号：US13228170

申请日：2011-09-08

申请人： Peter Cumming ,  Stephen Felix

发明人： Peter Cumming ,  Stephen Felix

IPC分类号： G06F9/00

CPC分类号： G06F9/441

摘要： An integrated circuit is disclosed herein. In one embodiment, the integrated circuit includes: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.

摘要翻译： 本文公开了集成电路。 在一个实施例中，集成电路包括：处理器; 可操作地耦合到所述处理器的多个外部引脚; 以及可操作地耦合到处理器的永久写入的存储器，所述存储器具有多个区域，每个区域存储用于引导处理器的一个或多个相应的引导属性。 处理器被编程为根据经由一个或多个外部引脚接收的指示来选择一个区域，以从所选择的区域检索一个或多个相应的引导属性，并使用一个或多个检索到的引导属性进行引导 。

公开(公告)号：US08024557B2

公开(公告)日：2011-09-20

申请号：US12127131

申请日：2008-05-27

申请人： Peter Cumming ,  Stephen Felix

发明人： Peter Cumming ,  Stephen Felix

IPC分类号： G06F9/00 ,  G06F9/24 ,  G06F15/177

CPC分类号： G06F9/441

摘要： An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.

摘要翻译： 一种集成电路，包括：处理器; 可操作地耦合到所述处理器的多个外部引脚; 以及可操作地耦合到所述处理器的永久写入的存储器，所述存储器具有多个区域，每个区域存储用于引导所述处理器的一个或多个相应的引导属性。 处理器被编程为根据经由一个或多个外部引脚接收到的指示来选择一个区域，以从所选择的区域检索一个或多个相应的引导属性，并使用一个或多个检索到的引导属性进行引导 。

公开(公告)号：US20090172383A1

公开(公告)日：2009-07-02

申请号：US12127131

申请日：2008-05-27

申请人： Peter Cumming ,  Stephen Felix

发明人： Peter Cumming ,  Stephen Felix

IPC分类号： G06F15/177 ,  G06F12/02

CPC分类号： G06F9/441

摘要： An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.

摘要翻译： 一种集成电路，包括：处理器; 可操作地耦合到所述处理器的多个外部引脚; 以及可操作地耦合到所述处理器的永久写入的存储器，所述存储器具有多个区域，每个区域存储用于引导所述处理器的一个或多个相应的引导属性。 处理器被编程为根据经由一个或多个外部引脚接收到的指示来选择一个区域，以从所选择的区域检索一个或多个相应的引导属性，并使用一个或多个检索到的引导属性进行引导 。

公开(公告)号：US08725999B2

公开(公告)日：2014-05-13

申请号：US13228170

申请日：2011-09-08

申请人： Peter Cumming ,  Stephen Felix

发明人： Peter Cumming ,  Stephen Felix

IPC分类号： G06F9/00 ,  G06F9/24 ,  G06F15/177

CPC分类号： G06F9/441

摘要： An integrated circuit is disclosed herein. In one embodiment, the integrated circuit includes: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.

摘要翻译： 本文公开了集成电路。 在一个实施例中，集成电路包括：处理器; 可操作地耦合到所述处理器的多个外部引脚; 以及可操作地耦合到所述处理器的永久写入的存储器，所述存储器具有多个区域，每个区域存储用于引导所述处理器的一个或多个相应的引导属性。 处理器被编程为根据经由一个或多个外部引脚接收到的指示来选择一个区域，以从所选择的区域检索一个或多个相应的引导属性，并使用一个或多个检索到的引导属性进行引导 。

公开(公告)号：US08782376B2

公开(公告)日：2014-07-15

申请号：US13219321

申请日：2011-08-26

申请人： Simon Knowles ,  Edward Andrews ,  Stephen Felix ,  Simon Huckett ,  Colman Hegarty

发明人： Simon Knowles ,  Edward Andrews ,  Stephen Felix ,  Simon Huckett ,  Colman Hegarty

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/30 ,  G06F9/345

CPC分类号： G06F9/30043 ,  G06F9/30163 ,  G06F9/30185 ,  G06F9/345 ,  G06F9/3889

摘要： A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

摘要翻译： 一种处理器，包括：第一和至少第二数据处理通道，其具有用于选择性地启用第二通道的使能逻辑; 用于基于相同存储访问指令的相同一个或多个地址操作数产生具有可变偏移的第一和第二存储地址的逻辑; 以及用于基于访问指令的相同的一个或多个寄存器指定器操作数，在第一数据处理通道的第一地址和寄存器之间以及第二地址和第二通道的相应寄存器之间传送数据的电路。 第一数据处理通道使用第一数据处理通道的一个或多个寄存器来执行操作，并且在使能的条件下，第二通道使用相应的一个或多个基于相同的一个或多个寄存器的相应操作 数据处理指令的操作数。

公开(公告)号：US20090172459A1

公开(公告)日：2009-07-02

申请号：US11967540

申请日：2007-12-31

申请人： Stephen Felix

发明人： Stephen Felix

IPC分类号： G06F1/08

CPC分类号： G06F1/08 ,  G11C7/00

摘要： A double data rate memory interface circuit for transferring data between an interfacing device and double data rate memory device. The interface circuit comprises a data input for receiving a data signal from a first of those devices, and a strobe input for receiving a strobe signal from that first device. The interface circuit also comprises delay circuitry for supplying the data and strobe signals to the other device with a timing offset introduced therebetween. The delay circuitry comprises a software programmable storage medium and a digitally controllable delay element coupled to the storage medium, the delay element being arranged to control the timing offset in dependence on a delay setting programmed into that storage medium.

摘要翻译： 一种用于在接口设备和双数据速率存储设备之间传送数据的双数据速率存储器接口电路。 接口电路包括用于从这些设备中的第一个接收数据信号的数据输入和用于从该第一设备接收选通信号的选通输入。 接口电路还包括用于将数据和选通信号提供给另一个设备的延迟电路，其间引入定时偏移。 所述延迟电路包括软件可编程存储介质和耦合到所述存储介质的数字可控延迟元件，所述延迟元件被布置为根据编程到所述存储介质中的延迟设置来控制所述定时偏移。

公开(公告)号：US20050276274A1

公开(公告)日：2005-12-15

申请号：US10855483

申请日：2004-05-28

申请人： Matthew Mattina ,  George Chrysos ,  Stephen Felix

发明人： Matthew Mattina ,  George Chrysos ,  Stephen Felix

IPC分类号： H04L12/427 ,  H04L12/43 ,  H04L12/56 ,  H04L12/28

CPC分类号： H04L12/43 ,  H04L12/427 ,  H04L47/10

摘要： Embodiments of the present invention are related in general to data flow control in a network and in particular to synchronous packet flow control in a ring interconnect. An embodiment of a method may include rejecting an arriving packet at a destination node on a semiconductor chip's ring interconnect, e.g., an unbuffered, synchronous ring interconnect, if all of the destination node's buffers are not available, leaving the rejected packet on the ring interconnect to continue traversing the ring, and accepting the rejected packet upon arrival at the destination node, if a buffer is available. In an alternate embodiment, a method may include tracking the rejected packet as the rejected packet traverses the ring interconnect. An embodiment of an apparatus may include a semiconductor chip having a bidirectional ring interconnect and multiple nodes coupled to the bidirectional ring interconnect. Each node may have a buffer to store packets that arrive on the ring interconnect, if the buffer is available, and to reject packets that arrive, if the buffer is not available. These embodiments provide efficient flow control of packets on unbuffered, synchronous ring interconnects. Exemplary applications include chip multiprocessing.

摘要翻译： 本发明的实施例一般涉及网络中的数据流控制，特别涉及环形互连中的同步分组流控制。 方法的实施例可以包括在半导体芯片的环形互连（例如，无缓冲的同步环形互连）上的目的地节点处拒绝到达的分组，如果所有目的地节点的缓冲器都不可用，则将拒绝的分组留在环形互连 继续遍历环，并且如果缓冲器可用，则在到达目的地节点时接受被拒绝的分组。 在替代实施例中，一种方法可以包括在拒绝的分组穿过环形互连时跟踪被拒绝的分组。 装置的实施例可以包括具有双向环互连和耦合到双向环互连的多个节点的半导体芯片。 每个节点可以具有缓冲器来存储到达环形互连上的分组，如果缓冲器可用，并且如果缓冲器不可用，则拒绝到达的分组。 这些实施例提供了在无缓冲的同步环互连上的分组的有效流控制。 示例性应用包括芯片多处理。

公开(公告)号：US06473334B1

公开(公告)日：2002-10-29

申请号：US10003335

申请日：2001-10-31

申请人： Daniel William Bailey ,  Stephen Felix ,  Stephen E. Liles

发明人： Daniel William Bailey ,  Stephen Felix ,  Stephen E. Liles

IPC分类号： G11C1100

CPC分类号： G11C8/16

摘要： A multi-ported SRAM memory cell includes a pair of inverters that holds the data bit. The state terminals of the memory cell connect via a separate read and write data path to the bit lines. The read bit lines connect to a pull-down transistor stack. The first transistor in the stack is gated by the word line, and the second transistor is gated by the state terminal of the memory cell. If the word line is asserted and the second transistor is turned on by the state of the memory cell, the bit line is connected to ground, thus pulling the bit line low. Conversely, if the second transmitter is not turned on, the bit line stays at a high voltage level. In a preferred embodiment, the memory cell is isolated from the pull-down transistor stack by an isolation buffer, such as an inverter, which inverts the voltage on the state terminal of the memory cell. The write data path couples to the memory cell through an access transistor, and also through a second gate that operates to restrict current leakage from the bit lines. In the preferred embodiment, the second gate comprises a current choke that limits current flow to the memory cell during a read operation. Alternatively, the second gate may comprise a transistor that is gated by a write enable signal.

摘要翻译： 多端口SRAM存储单元包括一对保持该数据位的反相器。 存储器单元的状态端子经由单独的读取和写入数据路径连接到位线。 读位线连接到下拉晶体管堆叠。 堆叠中的第一晶体管由字线选通，第二晶体管由存储单元的状态端选通。 如果字线被断言并且第二晶体管由存储单元的状态导通，则位线被连接到地，从而将位线拉低。 相反，如果第二个发射机没有接通，则位线保持在高电压电平。 在优选实施例中，存储单元通过诸如逆变器的隔离缓冲器与下拉晶体管堆叠隔离，该反相器使存储器单元的状态端子上的电压反相。 写入数据路径通过存取晶体管耦合到存储单元，并且还通过操作以限制来自位线的电流泄漏的第二栅极耦合。 在优选实施例中，第二栅极包括在读取操作期间限制电流流向存储器单元的电流扼流圈。 或者，第二栅极可以包括由写使能信号选通的晶体管。

公开(公告)号：US08827059B2

公开(公告)日：2014-09-09

申请号：US13411001

申请日：2012-03-02

申请人： Stephen Felix ,  Douglas Anderson ,  William Jubeck

发明人： Stephen Felix ,  Douglas Anderson ,  William Jubeck

IPC分类号： B65H75/44 ,  B65H16/02

摘要： An electrically powered mining vehicle including a frame rollingly supported on a surface for movement over the surface. An electric motor is coupled to the frame for proving power to the vehicle. A cable is electrically coupled to the electric motor for supplying electricity thereto and a cable management system is coupled to the frame and arranged to receive and payout the cable as the vehicle moves over the surface. A sheave bracket is coupled to the frame and arranged to direct the cable into the cable management system and includes a lower plate arranged substantially horizontally, a plurality of vertical rollers that are coupled to the lower plate and are arranged to guide the cable into the cable management system, and a horizontal roller that is coupled to the lower plate and arranged to elevate the cable above the lower plate.

公开(公告)号：US20130228386A1

公开(公告)日：2013-09-05

申请号：US13411001

申请日：2012-03-02

申请人： Stephen Felix ,  Douglas Anderson ,  William Jubeck

发明人： Stephen Felix ,  Douglas Anderson ,  William Jubeck

IPC分类号： B65H57/14 ,  B60P9/00 ,  B60L9/00

CPC分类号： B60L9/00 ,  B60L2200/36 ,  B65H57/14 ,  B65H2701/34

摘要： An electrically powered mining vehicle including a frame rollingly supported on a surface for movement over the surface. An electric motor is coupled to the frame for proving power to the vehicle. A cable is electrically coupled to the electric motor for supplying electricity thereto and a cable management system is coupled to the frame and arranged to receive and payout the cable as the vehicle moves over the surface. A sheave bracket is coupled to the frame and arranged to direct the cable into the cable management system and includes a lower plate arranged substantially horizontally, a plurality of vertical rollers that are coupled to the lower plate and are arranged to guide the cable into the cable management system, and a horizontal roller that is coupled to the lower plate and arranged to elevate the cable above the lower plate.

摘要翻译： 一种电动采矿车辆，其包括被滚动地支撑在表面上以在表面上移动的框架。 电动机耦合到框架以向车辆提供动力。 电缆电耦合到电动机用于向其供电，并且电缆管理系统耦合到框架并布置成当车辆在表面上移动时接收和支付电缆。 滑轮支架联接到框架并布置成将电缆引导到电缆管理系统中并且包括基本上水平布置的下板，多个垂直辊，其联接到下板并被布置成将电缆引导到电缆 管理系统以及耦合到下板并布置成将电缆提升到下板上方的水平辊。