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公开(公告)号：US07773733B2
公开(公告)日：2010-08-10
申请号：US11159614
申请日：2005-06-23
IPC分类号： H04M11/00
CPC分类号： H04M19/001
摘要： The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.
摘要翻译： 本发明提供了一种在DAA中的系统侧和线路侧电路之间的单个数字通信链路，能够承载数据信号并将大量电力传送到线路侧电路。 本发明包括系统侧接口电路，线路侧接口电路和包括变压器的隔离屏障。 每个接口电路能够连接到上游通信电路（线路侧或系统侧），从而可以接收要跨越隔离屏障传输到另一个接口电路的数据信号，并且其可以传递数据 跨隔离屏障的信号与另一个接口电路接收。 线路侧接口电路还可以包括整流器和存储装置。
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2.发明授权Digital correction of nonlinearity errors of multibit delta-sigma digital to analog converters 有权数字校正多位delta-sigma数模转换器的非线性误差公开(公告)号：US07362247B2
公开(公告)日：2008-04-22
申请号：US11430285
申请日：2006-05-08
申请人： Jesus Arias , Peter Kiss , Johannes G. Ransijn , James D. Yoder
发明人： Jesus Arias , Peter Kiss , Johannes G. Ransijn , James D. Yoder
IPC分类号： H03M1/10
CPC分类号： H03M3/388 , H03M1/0665 , H03M3/424 , H03M3/464
摘要： Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.
摘要翻译： 提供了用于误差反馈DAC的多位ADAC非线性的数字校正。 通过低分辨率校准ADC（CADC）估计多位ADAC的积分非线性（INL）误差（在线或离线）并存储在随机存取存储器（RAM）表中。 然后，INL值用于补偿ADAC在数字域中的失真。 当这种补偿与DWA等不匹配成形技术相结合时，可以显着放宽CADC的分辨率要求。 所提出的用于误差反馈调制器的修正电路的实现本质上是简单的，因为校正仅需要数字求和而不需要任何额外的数字滤波。
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3.发明申请Digital correction of nonlinearity errors of multibit delta-sigma digital to analog converters 有权数字校正多位delta-sigma数模转换器的非线性误差公开(公告)号：US20070109164A1
公开(公告)日：2007-05-17
申请号：US11430285
申请日：2006-05-08
申请人： Jesus Arias , Peter Kiss , Johannes Ransijn , James Yoder
发明人： Jesus Arias , Peter Kiss , Johannes Ransijn , James Yoder
IPC分类号： H03M3/00
CPC分类号： H03M3/388 , H03M1/0665 , H03M3/424 , H03M3/464
摘要： Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.
摘要翻译： 提供了用于误差反馈DAC的多位ADAC非线性的数字校正。 通过低分辨率校准ADC（CADC）估计多位ADAC的积分非线性（INL）误差（在线或离线）并存储在随机存取存储器（RAM）表中。 然后，INL值用于补偿ADAC在数字域中的失真。 当这种补偿与DWA等不匹配成形技术相结合时，可以显着放宽CADC的分辨率要求。 所提出的用于误差反馈调制器的修正电路的实现本质上是简单的，因为校正仅需要数字求和而不需要任何额外的数字滤波。
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公开(公告)号：US20070003055A1
公开(公告)日：2007-01-04
申请号：US11159614
申请日：2005-06-23
申请人： Boris Bark , Brad Grande , Peter Kiss , Johannes Ransijn , James Yoder
发明人： Boris Bark , Brad Grande , Peter Kiss , Johannes Ransijn , James Yoder
IPC分类号： H04M9/00
CPC分类号： H04M19/001
摘要： The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.
摘要翻译： 本发明提供了一种在DAA中的系统侧和线路侧电路之间的单个数字通信链路，能够承载数据信号并将大量电力传送到线路侧电路。 本发明包括系统侧接口电路，线路侧接口电路和包括变压器的隔离屏障。 每个接口电路能够连接到上游通信电路（线路侧或系统侧），从而可以接收要跨越隔离屏障传输到另一个接口电路的数据信号，并且其可以传递数据 跨隔离屏障的信号与另一个接口电路接收。 线路侧接口电路还可以包括整流器和存储装置。
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5.发明申请I/Q compensation of frequency dependent response mismatch in a pair of analog low-pass filters 有权一对模拟低通滤波器的频率相关响应失配的I / Q补偿公开(公告)号：US20050260949A1
公开(公告)日：2005-11-24
申请号：US10848187
申请日：2004-05-18
申请人： Peter Kiss , Vladimir Prodanov
发明人： Peter Kiss , Vladimir Prodanov
CPC分类号： H04B17/21
摘要： Frequency dependent I/Q imbalance in real I/Q filter pairs compensation may be performed using a simple compensation module, placed in the receiver/transmitter chain, with a gain adjustment coefficient and a delay adjustment coefficient. The gain adjustment coefficient may be determined by amplitude measurements conducted at a selected frequency near the center of the band-pass region of the filters. The delay adjustment coefficient may be determined by phase measurements conducted at a selected frequency near the edge of the band-pass region of the filters. Statistical analysis may be used to determine types of real filters that are better suited for the compensation method and to select the test frequencies that should be used.
摘要翻译： 实际I / Q滤波器对补偿中的频率依赖I / Q不平衡可以使用放大在接收机/发射机链中的简单补偿模块来执行，具有增益调整系数和延迟调整系数。 增益调整系数可以通过在滤波器的带通区域的中心附近的选定频率处进行的幅度测量来确定。 延迟调整系数可以通过在滤波器的带通区域的边缘附近的选定频率进行的相位测量来确定。 统计分析可用于确定更适合补偿方法的实际滤波器类型，并选择应使用的测试频率。
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6.发明授权Digital correction of nonlinearity errors of multibit delta-sigma digital to analog converters 有权数字校正多位delta-sigma数模转换器的非线性误差公开(公告)号：US07969335B2
公开(公告)日：2011-06-28
申请号：US12041204
申请日：2008-03-03
申请人： Jesus Arias , Peter Kiss , Johannes G. Ransijn , James D. Yoder
发明人： Jesus Arias , Peter Kiss , Johannes G. Ransijn , James D. Yoder
IPC分类号： H03M1/10
CPC分类号： H03M3/388 , H03M1/0665 , H03M3/424 , H03M3/464
摘要： Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.
摘要翻译： 提供了用于误差反馈DAC的多位ADAC非线性的数字校正。 通过低分辨率校准ADC（CADC）估计多位ADAC的积分非线性（INL）误差（在线或离线）并存储在随机存取存储器（RAM）表中。 然后，INL值用于补偿ADAC在数字域中的失真。 当这种补偿与DWA等不匹配成形技术相结合时，可以显着放宽CADC的分辨率要求。 所提出的用于误差反馈调制器的修正电路的实现本质上是简单的，因为校正仅需要数字求和而不需要任何额外的数字滤波。
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公开(公告)号：US07031690B2
公开(公告)日：2006-04-18
申请号：US10294411
申请日：2002-11-14
申请人： Vladimir Prodanov , Peter Kiss , Mihai Banu
发明人： Vladimir Prodanov , Peter Kiss , Mihai Banu
IPC分类号： H04B1/00
CPC分类号： H03H17/0277 , H03H2218/04
摘要： A complex low-pass filter that reduces the influence of component mismatch. The filter includes a first filter section for effecting a first single pole transfer function and a second filter section for effecting a second single pole transfer function, where the first and the second single pole transfer functions collectively define a conjugate pair of poles. In higher order low-pass filters, an optimal cascade order follows a shoestring pattern.
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8.发明申请Apparatus and method for preventing the bolt carrier of a firearm from moving forward after firing the last round of ammunition, and signaling when the firearm has run out of ammunition. 审中-公开用于在射击最后一轮弹药后防止枪支螺栓支架向前移动的装置和方法，以及当枪支用完弹药时发出信号。公开(公告)号：US20050000138A1
公开(公告)日：2005-01-06
申请号：US10708731
申请日：2004-03-21
申请人： Peter Kiss
发明人： Peter Kiss
CPC分类号： F41A17/36
摘要： The invention is designed to be fitted into the AK47-type semiautomatic firearms to provide a missing but vital feature of locking the reciprocating bolt assembly of said firearm after having chambered, fired and ejected the last cartridge from its removable magazine. The invention is designed to be installed into the receiver portion of the firearm as well as incorporating a modification into the removable magazine housing and follower. The invention consists of a number of components that will work in cooperation with each other to provide the above desired feature.
摘要翻译： 本发明被设计成安装在AK47型半自动枪械中，以提供锁定往返螺栓组件的缺失但重要的特征，该组件在从其可移除的刀库中进行腔室，燃烧和喷射最后一个药筒之后。 本发明被设计成安装在火器的接收器部分中，并将修改结合到可移除的刀库外壳和跟随器中。 本发明由能够相互协调工作以提供上述期望特征的多个部件组成。
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公开(公告)号：US20100246695A1
公开(公告)日：2010-09-30
申请号：US12794845
申请日：2010-06-07
IPC分类号： H04B3/00
CPC分类号： H04M19/001
摘要： The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.
摘要翻译： 本发明提供一种信号供电的集成电路（IC）。 IC包括集成电路管芯，其包括接地节点，供电节点和用于接收具有数据内容和预定能量的数字数据信号的第一终端。 形成在集成电路管芯上的接收缓冲器连接到第一终端并且能够接收与数字数据信号相关联的数据内容。 整流器也形成在集成电路管芯上。 整流器包括连接在第一端子和接地节点之间的第一二极管和连接在第一端子与供电节点之间的第二二极管。 整流器被配置为对数字数据信号进行整流，并将数字数据信号的至少一部分预定能量传递给供电节点。 第一和第二二极管中的每一个能够承受ESD冲击。
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10.发明申请公开(公告)号：US20080150773A1
公开(公告)日：2008-06-26
申请号：US12041204
申请日：2008-03-03
申请人： Jesus ARAIS , Peter Kiss , Johannes G. Ransijn , James D. Yoder
发明人： Jesus ARAIS , Peter Kiss , Johannes G. Ransijn , James D. Yoder
IPC分类号： H03M1/10
CPC分类号： H03M3/388 , H03M1/0665 , H03M3/424 , H03M3/464
摘要： Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.
摘要翻译： 提供了用于误差反馈DAC的多位ADAC非线性的数字校正。 通过低分辨率校准ADC（CADC）估计多位ADAC的积分非线性（INL）误差（在线或离线）并存储在随机存取存储器（RAM）表中。 然后，INL值用于补偿ADAC在数字域中的失真。 当这种补偿与DWA等不匹配成形技术相结合时，可以显着放宽CADC的分辨率要求。 所提出的用于误差反馈调制器的修正电路的实现本质上是简单的，因为校正仅需要数字求和而不需要任何额外的数字滤波。
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