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    Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device
    1.
    发明授权
    Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device 失效
    嵌入式NOR闪存过程与NAND单元和真正的逻辑兼容低电压器件

    公开(公告)号：US08455923B2

    公开(公告)日：2013-06-04

    申请号：US13135220

    申请日：2011-06-29

    申请人： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

    发明人： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

    IPC分类号： H01L27/118

    CPC分类号： H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66825 ,  H01L29/7881

    摘要： An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.

    摘要翻译： 由非易失性存储器阵列电路，逻辑电路和线性模拟电路形成的集成电路形成在基板上。 非易失性存储器阵列电路，逻辑电路和线性模拟电路由通过浅沟槽隔离形成的隔离区隔开。 非易失性存储器阵列电路形成为三重阱结构。 非易失性存储器阵列电路是由至少两个串联连接的浮栅晶体管形成的基于NAND的NOR存储器电路，使得浮栅晶体管中的至少一个用作选择栅极晶体管，以防止漏电流通过电荷保持晶体管， 电荷保持晶体管不被选择用于读取。 基于NAND的NOR存储器电路的每列与一个位线和一个源极线相关联并连接到一个位线和一个源极线。

    Novel embedded NOR flash memory process with NAND cell and true logic compatible low voltage device
    2.
    发明申请
    Novel embedded NOR flash memory process with NAND cell and true logic compatible low voltage device 失效
    新型嵌入式NOR闪存过程与NAND单元和真正逻辑兼容的低电压器件

    公开(公告)号：US20120001233A1

    公开(公告)日：2012-01-05

    申请号：US13135220

    申请日：2011-06-29

    申请人： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

    发明人： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

    IPC分类号： H01L23/52 ,  H01L21/8246

    CPC分类号： H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66825 ,  H01L29/7881

    摘要： An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.

    摘要翻译： 由非易失性存储器阵列电路，逻辑电路和线性模拟电路形成的集成电路形成在基板上。 非易失性存储器阵列电路，逻辑电路和线性模拟电路由通过浅沟槽隔离形成的隔离区隔开。 非易失性存储器阵列电路形成为三重阱结构。 非易失性存储器阵列电路是由至少两个串联连接的浮栅晶体管形成的基于NAND的NOR存储器电路，使得浮栅晶体管中的至少一个用作选择栅极晶体管，以防止漏电流通过电荷保持晶体管， 电荷保持晶体管不被选择用于读取。 基于NAND的NOR存储器电路的每列与一个位线和一个源极线相关联并连接到一个位线和一个源极线。

    NONVOLATILE MEMORY WITH A UNIFIED CELL STRUCTURE
    3.
    发明申请
    NONVOLATILE MEMORY WITH A UNIFIED CELL STRUCTURE 有权
    具有统一细胞结构的非易失性存储器

    公开(公告)号：US20110170357A1

    公开(公告)日：2011-07-14

    申请号：US13072281

    申请日：2011-03-25

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

    IPC分类号： G11C16/04

    CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

    摘要翻译： 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
    8.
    发明授权
    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
    单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案

    公开(公告)号：US07372736B2

    公开(公告)日：2008-05-13

    申请号：US11391662

    申请日：2006-03-28

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    IPC分类号： G11C16/04 ,  H01L29/76 ,  H01L23/544

    CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

    摘要翻译： 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。