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    Electronic circuit for providing a desired common mode voltage to a differential output of an amplifier stage
    1.
    发明授权
    Electronic circuit for providing a desired common mode voltage to a differential output of an amplifier stage 有权

    公开(公告)号：US06433634B1

    公开(公告)日：2002-08-13

    申请号：US09822474

    申请日：2001-03-30

    申请人： Pieter Gerrit Blanken ,  Stefan Eugene Josephus Menten

    发明人： Pieter Gerrit Blanken ,  Stefan Eugene Josephus Menten

    IPC分类号： H03F345

    摘要： An electronic circuit for supplying a common mode voltage to a differential output of an amplifier stage (AMPSTG). The common mode voltage at the terminals (1) and (2) is approximately equal to the reference voltage (VCM). Transistors (T1-T4) are biased in their linear region whereas transistors (T5-T8) are biased in their saturation region. In order to choose the lowest possible reference voltage (VCM), the dimensioning of the transistors (T1-T4) is such that the currents through the transistors (T1-T3) have equal current densities, and the current through the transistor (T4) has a current density which is a factor N smaller than the former current densities. The factor N is determined by the ratio of the nominal value of the current through the transistor (T1) and the minimum value of the current through the transistor (T1).

    Method and System for Determining Settings for Deep Brain Stimulation
    4.
    发明申请
    Method and System for Determining Settings for Deep Brain Stimulation 有权
    用于确定深脑刺激设置的方法和系统

    公开(公告)号：US20130030500A1

    公开(公告)日：2013-01-31

    申请号：US13581484

    申请日：2011-02-25

    申请人： Emil Toader ,  Hubert Cécile François Martens ,  Michel Marcel Jose Decre ,  Franciscus Paulus Maria Budzelaar ,  Pieter Gerrit Blanken ,  David James Anderson

    发明人： Emil Toader ,  Hubert Cécile François Martens ,  Michel Marcel Jose Decre ,  Franciscus Paulus Maria Budzelaar ,  Pieter Gerrit Blanken ,  David James Anderson

    IPC分类号： A61N1/36

    CPC分类号： A61N1/36139 ,  A61N1/00 ,  A61N1/0534 ,  A61N1/36185

    摘要： A method and a control system (20) are provided for determining a relation between stimulation settings for a brain stimulation probe (10) and a corresponding V-field. The brain stimulation probe (10) comprises multiple stimulation electrodes (11). The V-field is an electrical field in brain tissue surrounding the stimulation electrodes (11). The method comprises sequentially applying a test current to n stimulation electrodes (11), n being a number between 2 and the number of stimulation electrodes (11) of the brain stimulation probe (10), for each test current at one of the n stimulation electrodes (11), measuring a resulting excitation voltage at m stimulation electrodes, m being a number between 2 and the number of stimulation electrodes (11) of the brain stimulation probe (10), from the stimulation settings and the measured excitation voltages, deriving an (m*{acute over (η)}) coupling matrix, an element (q, p) in the coupling matrix reflecting an amount of electrical impedance between two of the stimulation electrodes (11), and using the coupling matrix for determining the relation between the stimulation settings and the corresponding V-field.

    摘要翻译： 提供一种方法和控制系统（20），用于确定脑刺激探针（10）的刺激设置与相应的V场之间的关系。 脑刺激探针（10）包括多个刺激电极（11）。 V场是围绕刺激电极（11）的脑组织中的电场。 所述方法包括对n个刺激电极（11）依次施加测试电流，n是在刺激探针（10）的刺激电极（11）的数量之间的数量，对于在n个刺激之一的每个测试电流 电极（11），根据刺激设置和所测量的激发电压，测量m个刺激电极处的所得激励电压，m为2个与脑刺激探针（10）的刺激电极（11）的数量之间的数字，导出 耦合矩阵中的元素（q，p），反映两个刺激电极（11）之间的电阻抗的量，并且使用用于确定的耦合矩阵 刺激设置与相应V字段之间的关系。

    Parallel arranged power supplies
    5.
    发明授权
    Parallel arranged power supplies 有权
    并联电源

    公开(公告)号：US07808225B2

    公开(公告)日：2010-10-05

    申请号：US11547416

    申请日：2005-03-24

    申请人： Ralf Burdenski ,  Pieter Gerrit Blanken ,  Giuseppe Grillo ,  Derk Reefman

    发明人： Ralf Burdenski ,  Pieter Gerrit Blanken ,  Giuseppe Grillo ,  Derk Reefman

    IPC分类号： G05F1/445

    CPC分类号： H02M3/1584 ,  Y10T307/50

    摘要： A power supply system comprises a parallel arrangement of a first switched mode power supply (1) which has a first system bandwidth (LB 1) and a second switched mode power supply (2) which has a second system bandwidth (LB2) covering higher frequencies than the first system bandwidth (LB 1). The first switched mode power supply (1) is dimensioned to supply a first maximal output power (P1m), the second switched mode power supply (2) is dimensioned to supply a second maximal output power (P2m) being smaller than the first maximal output power (P1m). A control circuit (3) varies a reference voltage (Vr) of both the first switched mode power supply (1) and the second switched mode power supply (2) to obtain a corresponding variation of an output voltage (Vout) of the parallel arrangement.

    摘要翻译： 电源系统包括具有第一系统带宽（LB1）和第二开关模式电源（2）的第一开关模式电源（1）的并联布置，所述第一开关模式电源具有覆盖较高频率的第二系统带宽（LB2） 比第一个系统带宽（LB 1）。 第一开关模式电源（1）的尺寸设定为提供第一最大输出功率（P1m），第二开关模式电源（2）的尺寸被设计成提供小于第一最大输出功率的第二最大输出功率（P2m） 功率（P1m）。 控制电路（3）改变第一开关模式电源（1）和第二开关模式电源（2）两者的参考电压（Vr），以获得并联装置的输出电压（Vout）的相应变化 。

    Semiconductor switch with reliable blackout behavior and low control power
    6.
    发明授权
    Semiconductor switch with reliable blackout behavior and low control power 有权
    具有可靠的停电行为和低控制功率的半导体开关

    公开(公告)号：US09065429B2

    公开(公告)日：2015-06-23

    申请号：US14111836

    申请日：2012-04-10

    申请人： Pieter Gerrit Blanken ,  Peter Luerkens ,  Matthias Wendt ,  Carsten Deppe

    发明人： Pieter Gerrit Blanken ,  Peter Luerkens ,  Matthias Wendt ,  Carsten Deppe

    IPC分类号： H03L7/00 ,  H03K3/012 ,  H03K17/687 ,  H03K17/691

    CPC分类号： H03K3/012 ,  H03K17/6874 ,  H03K17/691 ,  H03K2217/0081

    摘要： The present invention relates to a bidirectional semiconductor switch (M1, M2) with extremely low control power consumption and a bootstrap circuit which allows reliable start of operation of the switch and the hosting device after unlimited duration of mains interruptions. Intelligent control options are provided by operating from a small energy storage and no extra means are required to recover from a depleted energy storage condition. The absence of audible noise and mechanical wear also enables more frequent recharging cycles and allows smaller and thus cheaper energy storage components.

    摘要翻译： 本发明涉及具有极低控制功率消耗的双向半导体开关（M1，M2）和自举电路，其允许开关和主机设备在无限期的电源中断之后可靠地开始操作。 通过从小型能量存储器操作提供智能控制选项，并且不需要额外的方法来从耗尽的能量存储状态恢复。 没有可听见的噪音和机械磨损也使更频繁的充电循环，并且允许更小且因此更便宜的储能部件。

    Method and system for determining settings for deep brain stimulation
    7.
    发明授权
    Method and system for determining settings for deep brain stimulation 有权
    用于确定深部脑刺激设置的方法和系统

    公开(公告)号：US08929992B2

    公开(公告)日：2015-01-06

    申请号：US13581484

    申请日：2011-02-25

    申请人： Emil Toader ,  Hubert Cécile François Martens ,  Michel Marcel Jose Decre ,  Franciscus Paulus Maria Budzelaar ,  Pieter Gerrit Blanken ,  David James Anderson

    发明人： Emil Toader ,  Hubert Cécile François Martens ,  Michel Marcel Jose Decre ,  Franciscus Paulus Maria Budzelaar ,  Pieter Gerrit Blanken ,  David James Anderson

    IPC分类号： A61N1/36 ,  A61N1/05 ,  A61N1/00

    CPC分类号： A61N1/36139 ,  A61N1/00 ,  A61N1/0534 ,  A61N1/36185

    摘要： A method and a control system (20) are provided for determining a relation between stimulation settings for a brain stimulation probe (10) and a corresponding V-field. The brain stimulation probe (10) comprises multiple stimulation electrodes (11). The V-field is an electrical field in brain tissue surrounding the stimulation electrodes (11). The method comprises sequentially applying a test current to n stimulation electrodes (11), n being a number between 2 and the number of stimulation electrodes (11) of the brain stimulation probe (10), for each test current at one of the n stimulation electrodes (11), measuring a resulting excitation voltage at m stimulation electrodes, m being a number between 2 and the number of stimulation electrodes (11) of the brain stimulation probe (10), from the stimulation settings and the measured excitation voltages, deriving an (m*{acute over (η)}) coupling matrix, an element (q, p) in the coupling matrix reflecting an amount of electrical impedance between two of the stimulation electrodes (11), and using the coupling matrix for determining the relation between the stimulation settings and the corresponding V-field.

    摘要翻译： 提供一种方法和控制系统（20），用于确定脑刺激探针（10）的刺激设置与相应的V场之间的关系。 脑刺激探针（10）包括多个刺激电极（11）。 V场是围绕刺激电极（11）的脑组织中的电场。 所述方法包括对n个刺激电极（11）依次施加测试电流，n是在刺激探针（10）的刺激电极（11）的数量之间的数量，对于在n个刺激之一的每个测试电流 电极（11），根据刺激设置和所测量的激发电压，测量m个刺激电极处的所得激励电压，m为2个与脑刺激探针（10）的刺激电极（11）的数量之间的数字，导出 耦合矩阵中的元素（q，p），反映两个刺激电极（11）之间的电阻抗的量，并且使用用于确定的耦合矩阵 刺激设置与相应V字段之间的关系。

    Common mode voltage generation at a differential output of an amplifier
    8.
    发明授权
    Common mode voltage generation at a differential output of an amplifier 有权
    在放大器的差分输出端产生共模电压

    公开(公告)号：US06987421B2

    公开(公告)日：2006-01-17

    申请号：US10828063

    申请日：2004-04-20

    申请人： Pieter Gerrit Blanken

    发明人： Pieter Gerrit Blanken

    IPC分类号： H03F3/45 ,  H03K19/0175

    CPC分类号： H03F3/45192 ,  H03F2203/45398 ,  H03F2203/45401

    摘要： A common mode voltage generating circuit has a first and a second output terminal (O1, O2) to supply a common mode voltage (Vcm) to a differential output of an amplifier stage (AMP). A first FET (T1) and a second FET (T2) have interconnected drains, and both have a source coupled to a supply terminal (Vss). A third FET (T3) has a source coupled to the drain of T1, a drain coupled to O1 and to a gate of T1. A fourth FET (T4) has a source coupled to a drain of T2, a drain coupled to O2 and to a gate of T2. A fifth FET (T5) has a gate for receiving a first reference voltage (VI), and a sixth FET (T6) has a source coupled to the drain of T5, a drain receiving a current (2I) from a current source (CS4), wherein the drain and the gate of T6 are interconnected. T3, T4 and T6 have interconnected gates and are biased to operate in their saturation region. T1, T2 and T5 are biased to operate in their linear regions. The common mode voltage generating circuit further comprises a seventh FET (T7) with a source coupled to Vss, a drain coupled to the drain of T5, and with a gate which receives a second reference voltage (Vh). T7 is biased to operate in its linear region. Bipolar transistors may be used instead of FET's.

    摘要翻译： 共模电压发生电路具有第一和第二输出端（O 1，O 2），以向放大器级（AMP）的差分输出端提供共模电压（Vcm）。 第一FET（T 1）和第二FET（T 2）具有互连的漏极，并且它们都具有耦合到电源端子（Vss）的源极。 第三FET（T 3）具有耦合到T 1的漏极的源极，耦合到O 1的漏极和T 1的栅极。 第四FET（T 4）具有耦合到T 2的漏极的源极，耦合到O 2的漏极和T 2的栅极。 第五FET（T 5）具有用于接收第一参考电压（VI）的栅极，并且第六FET（T6）具有耦合到T 5的漏极的源极，从第一FET接收电流（2I）的漏极 电流源（CS 4），其中T 6的漏极和栅极互连。 T 3，T 4和T 6具有互连的栅极并被偏置以在其饱和区域中操作。 T 1，T 2和T 5被偏置以在其线性区域中操作。 共模电压产生电路还包括具有耦合到Vss的源极的第七FET（T 7），耦合到T 5的漏极的漏极和接收第二参考电压（Vh）的栅极。 T 7被偏置以在其线性区域中操作。 可以使用双极晶体管代替FET。

    Electronic circuit comprising an amplifier with improved transient speed
    9.
    发明授权
    Electronic circuit comprising an amplifier with improved transient speed 失效
    电子电路包括具有改善的瞬态速度的放大器

    公开(公告)号：US06717472B2

    公开(公告)日：2004-04-06

    申请号：US10116500

    申请日：2002-04-04

    申请人： Pieter Gerrit Blanken ,  Franciscus Adrianus Cornelis Maria Schoofs ,  Mike Hendrikus Splithof ,  Paulus Petrus Franciscus Maria Bruin

    发明人： Pieter Gerrit Blanken ,  Franciscus Adrianus Cornelis Maria Schoofs ,  Mike Hendrikus Splithof ,  Paulus Petrus Franciscus Maria Bruin

    IPC分类号： H03G320

    CPC分类号： H03F3/3035 ,  H03F3/45201

    摘要： An electronic circuit comprising an amplifier includes an output terminal (OUT) for supplying an output signal (Vout) to a load, the amplifier comprising an output transistor (N2, P1) having a first main terminal coupled to a supply voltage terminal (VSS, VDD) of the amplifier, a second main terminal coupled to the output terminal (OUT), and a control terminal. In order to avoid that the output transistor (N2, P1) can enter its linear state which would cause the amplifier to act unacceptably slow for some purposes, the electronic circuit further comprises a controller adapted to prevent the output transistor (N2, P1) to enter its linear state whereby the controller is arranged for reducing a control voltage (Vcntrl) between the control terminal and the first main terminal when an output voltage (Vout) between the second main terminal and the first main terminal is below a defined level.

    摘要翻译： 包括放大器的电子电路包括用于向负载提供输出信号（Vout）的输出端（OUT），所述放大器包括输出晶体管（N2，P1），其具有耦合到电源电压端子（VSS， VDD），耦合到输出端（OUT）的第二主端子和控制端子。 为了避免输出晶体管（N2，P1）进入其线性状态，这将导致放大器对于某些目的而不能接受地变慢，电子电路还包括控制器，其适于防止输出晶体管（N2，P1） 进入其线性状态，由此，当第二主端子和第一主端子之间的输出电压（Vout）低于限定电平时，控制器布置成用于减小控制端子与第一主端子之间的控制电压（Vcntr1）。