公开(公告)号：US6141711A

公开(公告)日：2000-10-31

申请号：US769998

申请日：1996-12-19

申请人： Pranay D. Shah ,  Kenneth C. Ma ,  Jeffrey A. Hawkey ,  Kenneth J. Kotlowski

发明人： Pranay D. Shah ,  Kenneth C. Ma ,  Jeffrey A. Hawkey ,  Kenneth J. Kotlowski

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4081 ,  G06F13/4027

摘要： A secondary bus controller allows for hot insertion and ejection of devices from the secondary bus without ceasing operations or halting software in the host computer. When a device is to be inserted a signal is sent to the secondary bus controller. The secondary bus controller suspends operation of the secondary bus, placing devices on the secondary bus in stasis. An interrupt handler reconfigures the system for the newly inserted card once it has been inserted. Attempts to access devices on the secondary bus during the insertion process may be met with a retry signal until insertion is complete. The ejection process follows similar steps, isolating and suspending operations on the secondary bus and triggering an interrupt routine in the host processor to reconfigure the system. The host processor and primary busses, along with the secondary bus controller remain active throughout the insertion or ejection processes. Thus, applications running on the host computer need not be terminated during insertion or ejection. The present invention has particular application to network server computer systems.

摘要翻译： 辅助总线控制器允许从辅助总线热插拔设备，而不停止主机中的操作或停止软件。 当要插入设备时，信号被发送到辅助总线控制器。 辅助总线控制器暂停辅助总线的操作，将设备放在辅助总线上停滞。 中断处理程序重新配置新插入的卡的系统。 在插入过程中尝试访问辅助总线上的设备可能会遇到重试信号，直到插入完成。 弹出过程遵循类似的步骤，在辅助总线上进行隔离和暂停操作，并触发主机处理器中的中断程序来重新配置系统。 主处理器和主总线以及辅助总线控制器在插入或弹出过程中保持活动。 因此，在插入或弹出时不需要终止在主机上运行的应用程序。 本发明特别适用于网络服务器计算机系统。

公开(公告)号：US08587600B1

公开(公告)日：2013-11-19

申请号：US11119561

申请日：2005-05-02

申请人： Brett A. Tischler ,  Kenneth J. Kotlowski ,  Willard S. Briggs

发明人： Brett A. Tischler ,  Kenneth J. Kotlowski ,  Willard S. Briggs

IPC分类号： G09G5/36 ,  G06F13/00

CPC分类号： G09G5/363 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2360/121

摘要： Systems and methods for cache-based compressed display data storage are provided. One system includes memory operable to store compressed display data, a processor comprising a processing core and a cache, a cache storage module operably coupled to the memory and the processor, wherein the cache storage module is to initiate a storage of at least a portion of the compressed display data in the cache in response to an indication that the processing core is in an inactive mode. One method comprises, in response to an indication that a processor is in an inactive mode, transferring compressed display data from a frame buffer in memory to a cache associated with the processor, obtaining a first compressed display data from the cache, and decompressing the first compressed display data to generate a first uncompressed display data.

摘要翻译： 提供了基于缓存的压缩显示数据存储的系统和方法。 一个系统包括可操作以存储压缩显示数据的存储器，包括处理核心和高速缓存的处理器，可操作地耦合到存储器和处理器的高速缓存存储模块，其中高速缓存存储模块将启动存储至少一部分 响应于处理核心处于非活动模式的指示，缓存中的压缩显示数据。 一种方法包括响应于处理器处于非活动模式的指示，将压缩显示数据从存储器中的帧缓冲器传送到与处理器相关联的高速缓存器，从高速缓存获取第一压缩显示数据，并解压缩第一 压缩显示数据以产生第一未压缩显示数据。

公开(公告)号：US07185128B1

公开(公告)日：2007-02-27

申请号：US10714584

申请日：2003-11-14

申请人： Kenneth J. Kotlowski ,  Brett Tischler

发明人： Kenneth J. Kotlowski ,  Brett Tischler

IPC分类号： G06F13/00 ,  G06F9/44

CPC分类号： G06F13/372

摘要： There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus devices; 2) a plurality of output ports for transmitting data to the plurality of bus devices; and 3) a controller for reading N routing associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in the N routing bits to a first designated value. The controller, in response to a determination that the first ID value does not equal the first designated value: 1) realigns the N routing bits such that remaining ones of the N-M bits outside the predetermined M-bit field are moved into the predetermined M-bit field and 2) transmits the realigned N routing bits via a first one of the plurality of output ports identified by the first ID value.

摘要翻译： 公开了一种用于在多个总线设备之间传送机器特定寄存器（MSR）请求的总线接口单元。 总线接口单元包括：1）多个输入端口，用于从多个总线设备接收传入的MSR请求; 2）多个输出端口，用于向多个总线装置发送数据; 以及3）控制器，用于读取与第一接收的MSR请求相关联的N路由，并将N个路由比特中的预定M比特字段中的第一标识（ID）值与第一指定值进行比较。 控制器响应于第一ID值不等于第一指定值的确定：1）重新排列N个路由比特，使得预定M比特字段外的NM比特中的剩余的比特移动到预定的M- 位域，以及2）经由由所述第一ID值标识的所述多个输出端口中的第一个发送所述重新排列的N个路由位。

公开(公告)号：US07043593B1

公开(公告)日：2006-05-09

申请号：US10425574

申请日：2003-04-29

申请人： Brett A. Tischler ,  Kenneth J. Kotlowski

发明人： Brett A. Tischler ,  Kenneth J. Kotlowski

IPC分类号： G06F13/00

CPC分类号： G06F13/161

摘要： A master unit and a slave unit in a data processor are coupled together by a data bus. The master unit sends data transactions to the slave unit through the data bus and the slave unit executes the data transactions. The present invention comprises an apparatus and method for executing a data transaction either (1) by executing the data transaction “in order” with respect to other data transactions received by the slave unit, or (2) by executing the data transaction “out of order” with respect to other data transactions received by the slave unit. The master unit assigns a priority identifier to each data transaction. The slave unit reads the priority identifier to determine whether to execute the data transaction “in order” or “out of order” with respect to the other data transactions.

摘要翻译： 数据处理器中的主单元和从单元由数据总线耦合在一起。 主单元通过数据总线向从单元发送数据事务，从单元执行数据事务。 本发明包括一种用于执行数据事务的装置和方法（1）通过相对于从单元接收到的其他数据事务执行数据事务“按顺序”，或者（2）通过执行数据事务“ 相对于从单元接收到的其他数据事务的顺序。 主单元为每个数据事务分配一个优先级标识符。 从单元读取优先级标识符，以确定是否相对于其他数据事务执行数据事务“按顺序”或“乱序”。

公开(公告)号：US07576771B1

公开(公告)日：2009-08-18

申请号：US11075303

申请日：2005-03-08

申请人： Kenneth J. Kotlowski ,  Daniel Daugherty

发明人： Kenneth J. Kotlowski ,  Daniel Daugherty

IPC分类号： H04N17/02 ,  H04N5/21 ,  H04N5/08

CPC分类号： H04N17/02 ,  H04N5/04

摘要： Video control signals are received at a video input port of a system. A determination is made whether the video control signals are valid or invalid. When video control signals represent a valid video signal, providing a delayed representation of a control signal to a synchronization input of a display engine of the system, and when the video control signals represent an invalid video signal, providing a an alternative signal to the synchronization input of the display engine.

摘要翻译： 在系统的视频输入端口处接收视频控制信号。 确定视频控制信号是有效还是无效。 当视频控制信号表示有效的视频信号时，向系统的显示引擎的同步输入提供控制信号的延迟表示，并且当视频控制信号表示无效视频信号时，向同步提供替代信号 输入显示引擎。

公开(公告)号：US5274822A

公开(公告)日：1993-12-28

申请号：US547352

申请日：1990-07-02

申请人： Richard L. Stanton ,  Kenneth J. Kotlowski

发明人： Richard L. Stanton ,  Kenneth J. Kotlowski

IPC分类号： G06F13/364 ,  G06F13/14

CPC分类号： G06F13/364

摘要： A fast centralized arbitrator for avoiding contention between up to eight processors or other smart devices having access to a shared computer facility. Each of the processors or smart devices is assigned a unique three digit octal formatted priority level. A first set of 1-of-8 decoders, AND gates and a prioritizer circuit are employed to determine the priority level of the highest priority device requesting access to the shared facility. A second set of 1-of-8 decoders, each having associated therewith a set of OR gates for combining the decoder outputs with the outputs of the prioritizer circuit and an AND gate for combining the outputs of the set of OR gates, are employed to generate a set of acknowledge signals for the smart devices.

摘要翻译： 一种快速集中仲裁器，用于避免多达八个处理器或具有访问共享计算机设施的其他智能设备之间的争用。 每个处理器或智能设备都被分配一个唯一的三位八进制格式的优先级。 采用第一组1/8解码器，与门和优先化电路来确定请求接入共享设施的最高优先级设备的优先级。 第二组1/8解码器，每一个都具有相关联的一组OR门，用于将解码器输出与优先化器电路的输出和用于组合OR门的输出的“与”门组合。 为智能设备生成一组确认信号。