公开(公告)号：US20130126509A1

公开(公告)日：2013-05-23

申请号：US13351741

申请日：2012-01-17

申请人： QIYANG HE ,  Yiying Zhang

发明人： QIYANG HE ,  Yiying Zhang

IPC分类号： H05B1/00

CPC分类号： H01L21/67115 ,  H01L21/67248 ,  H01L21/6831

摘要： This invention discloses a reaction apparatus for wafer treatment, an electrostatic chuck and a wafer temperature control method, in the field of semiconductor processing. The electrostatic chuck comprises an insulating layer for supporting a wafer and a lamp array disposed in the insulating layer. Each lamp of the lamp array can be independently controlled to turn on and off and/or to adjust the output power. By controlling the on/off switch and/or output power of each lamp of the lamp array the temperature of the wafer held on the ESC is adjusted and temperature non-uniformity can be more favourably adjusted, greatly improving wafer temperature uniformity, particularly alleviating non-radial temperature non-uniformity.

摘要翻译： 本发明公开了一种在半导体处理领域中的晶片处理用反应装置，静电卡盘和晶片温度控制方法。 静电卡盘包括用于支撑晶片的绝缘层和设置在绝缘层中的灯阵列。 灯阵列的每个灯可以被独立地控制以打开和关闭和/或调节输出功率。 通过控制灯阵列的每个灯的开/关开关和/或输出功率，调节保持在ESC上的晶片的温度，并且可以更好地调节温度不均匀性，极大地提高晶片温度均匀性，特别是减轻非 - 镭温度不均匀。

公开(公告)号：US20120309151A1

公开(公告)日：2012-12-06

申请号：US13293030

申请日：2011-11-09

申请人： Yiying Zhang ,  Qiyang He

发明人： Yiying Zhang ,  Qiyang He

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3086 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

摘要： Method of fabricating a semiconductor device includes forming a gate having a first material on a substrate and forming a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. The substrate is dry etched using the layer of second material and the sidewall spacers as a mask forming a recess in the substrate between two adjacent gates. A liner oxide layer is formed on inner walls of the recess. The liner oxide layer is removed by isotropic wet etching. Orientation selective wet etching is performed on the recess to shape the inner wall of the recess so as to cause the inner wall of the recess to be sigma-shaped. By removing the substrate portions having lattice defects due to dry etching through oxidation and wet etching, defect-free epitaxial growth performance is realized.

摘要翻译： 制造半导体器件的方法包括在衬底上形成具有第一材料的栅极并形成覆盖栅极的第二材料层。 侧壁间隔件形成在门的相对侧上。 使用第二材料层和侧壁间隔物作为在两个相邻栅极之间的衬底中形成凹陷的掩模进行干蚀刻。 衬垫氧化物层形成在凹槽的内壁上。 通过各向同性湿蚀刻除去衬里氧化物层。 在凹部上进行取向选择性湿蚀刻，以形成凹部的内壁，从而使凹部的内壁成为西格玛形状。 通过通过氧化和湿蚀刻去除由于干蚀刻而具有晶格缺陷的衬底部分，实现了无缺陷的外延生长性能。

公开(公告)号：US08952297B2

公开(公告)日：2015-02-10

申请号：US13351741

申请日：2012-01-17

申请人： Qiyang He ,  Yiying Zhang

发明人： Qiyang He ,  Yiying Zhang

IPC分类号： F27B5/14 ,  H01L21/67 ,  H01L21/683 ,  H05B1/00

CPC分类号： H01L21/67115 ,  H01L21/67248 ,  H01L21/6831

摘要： This invention discloses a reaction apparatus for wafer treatment, an electrostatic chuck and a wafer temperature control method, in the field of semiconductor processing. The electrostatic chuck comprises an insulating layer for supporting a wafer and a lamp array disposed in the insulating layer. Each lamp of the lamp array can be independently controlled to turn on and off and/or to adjust the output power. By controlling the on/off switch and/or output power of each lamp of the lamp array the temperature of the wafer held on the ESC is adjusted and temperature non-uniformity can be more favorably adjusted, greatly improving wafer temperature uniformity, particularly alleviating non-radial temperature non-uniformity.

摘要翻译： 本发明公开了一种在半导体处理领域中的晶片处理用反应装置，静电卡盘和晶片温度控制方法。 静电卡盘包括用于支撑晶片的绝缘层和设置在绝缘层中的灯阵列。 灯阵列的每个灯可以被独立地控制以打开和关闭和/或调节输出功率。 通过控制灯阵列的每个灯的开/关开关和/或输出功率，调节保持在ESC上的晶片的温度，并且可以更好地调节温度不均匀性，极大地提高晶片温度均匀性，特别是减轻非 - 镭温度不均匀。

公开(公告)号：US08507379B2

公开(公告)日：2013-08-13

申请号：US13240820

申请日：2011-09-22

申请人： Yiying Zhang ,  Qiyang He

发明人： Yiying Zhang ,  Qiyang He

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L21/441

CPC分类号： H01L21/28079 ,  H01L21/76802 ,  H01L21/76805 ,  H01L29/495 ,  H01L29/66545

摘要： A semiconductor device and a manufacturing method thereof are disclosed. The method comprises: providing a substrate with a first dielectric layer and a gate, wherein the gate is embedded in the first dielectric layer and an upper portion of the gate is an exposed first metal; and covering only the exposed first metal with a conductive material that is harder to be oxidized than the first metal by a selective deposition. An advantage of the present invention is that the metal of the upper surface of the gate is prevented from being oxidized by covering the metal gate with the conductive material that is relatively harder to be oxidized, thereby facilitating the formation of an effective electrical connection to the gate.

摘要翻译： 公开了一种半导体器件及其制造方法。 该方法包括：向基板提供第一介电层和栅极，其中栅极嵌入在第一介电层中，栅极的上部是暴露的第一金属; 并且通过选择性沉积仅用暴露的第一金属覆盖比第一金属更难被氧化的导电材料。 本发明的优点在于，通过用相对较难氧化的导电材料覆盖金属栅，防止栅极上表面的金属被氧化，从而有助于形成有效的电连接到 门。

公开(公告)号：US08759179B2

公开(公告)日：2014-06-24

申请号：US13243902

申请日：2011-09-23

申请人： Yiying Zhang ,  Qiyang He

发明人： Yiying Zhang ,  Qiyang He

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L29/94 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7831 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L29/66825

摘要： This disclosure relates to a method of forming a gate pattern and a semiconductor device. The gate pattern comprises a plurality of parallel gate bars, and each gate bar is broken up by gaps. The method comprises: making an etching characteristic of a gate material layer at least at positions where the gaps are to be formed different from that at remaining positions; forming a plurality of parallel openings in a second resist layer; performing a first etching process on the gate material layer with the second resist layer as a mask, wherein portions of the gate material layer at least at the positions where the gaps are to be formed are selectively left; and performing a second etching process on the gate material layer so as to selectively remove the portions. This method can more accurately control the shape and size of the gate pattern.

摘要翻译： 本公开涉及形成栅极图案和半导体器件的方法。 栅极图案包括多个平行栅极条，并且每个栅条被间隙分解。 该方法包括：至少在要形成间隙的位置处形成不同于剩余位置处的栅极材料层的蚀刻特性; 在第二抗蚀剂层中形成多个平行的开口; 在栅极材料层上进行第一蚀刻工艺，其中第二抗蚀剂层作为掩模，选择性地留下栅极材料层至少在要形成间隙的位置的部分; 以及对所述栅极材料层进行第二蚀刻处理，以选择性地去除所述部分。 该方法可以更准确地控制栅极图案的形状和尺寸。

公开(公告)号：US08450167B2

公开(公告)日：2013-05-28

申请号：US13293052

申请日：2011-11-09

申请人： Qiyang He ,  Yiying Zhang

发明人： Qiyang He ,  Yiying Zhang

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3086 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7848

摘要： A method of fabricating semiconductor device includes forming a plurality of gates on a substrate, forming a top layer on a top surface of each gate, forming sidewall spacers on opposite sides of each gate, and forming sacrificial spacers on the sidewall spacers. The method further includes performing a dry etching process on the substrate using the top layer and the sacrificial spacers as a mask to form a recess of a first width in the substrate between two adjacent gates, performing an isotropic wet etching process on the recess to expand the first width to a second width, and performing an orientation selective wet etching process on the recess to shape the rectangular-shaped recess into a Σ-shaped recess.

摘要翻译： 制造半导体器件的方法包括在衬底上形成多个栅极，在每个栅极的顶表面上形成顶层，在每个栅极的相对侧上形成侧壁隔离物，以及在侧壁间隔物上形成牺牲隔离物。 该方法还包括使用顶层和牺牲隔离物作为掩模在衬底上进行干蚀刻处理，以在两个相邻栅极之间的衬底中形成第一宽度的凹槽，在凹部上进行各向同性的湿蚀刻工艺以扩展 第一宽度到第二宽度，并且在凹部上执行取向选择性湿蚀刻工艺以将矩形凹槽形成为Sigma形凹部。

公开(公告)号：US20120309150A1

公开(公告)日：2012-12-06

申请号：US13293001

申请日：2011-11-09

申请人： Yiying Zhang ,  Qiyang He

发明人： Yiying Zhang ,  Qiyang He

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

摘要： A method of fabricating a semiconductor device is provided. The method includes forming a gate having a first material on a substrate and a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. A characteristic of a portion of the substrate between adjacent sidewall spacers is changed using the layer of second material and the sidewall spacers as a mask. An isotropic wet etch process is performed to remove the substrate portion with a changed characteristic to form a recess in the substrate. An orientation selective wet etching process is performed on the recess to shape the inner walls of the recess into sigma-shape. Changing a substrate characteristic in conjunction with isotropic wet etching prevents the substrate from being damaged, and therefore can obtain defect free epitaxial SiGe growth performance.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成具有第一材料的栅极和覆盖栅极的第二材料层。 侧壁间隔件形成在门的相对侧上。 使用第二材料层和侧壁间隔物作为掩模来改变相邻侧壁间隔物之间​​的衬底的一部分的特性。 执行各向同性湿法蚀刻工艺以以改变的特性去除衬底部分，以在衬底中形成凹陷。 在凹部上执行取向选择性湿蚀刻工艺，以将凹陷的内壁形成为西格玛形状。 结合各向同性湿蚀刻改变衬底特性防止衬底受损，因此可获得无缺陷的外延SiGe生长性能。

公开(公告)号：US09349862B2

公开(公告)日：2016-05-24

申请号：US13293001

申请日：2011-11-09

申请人： Yiying Zhang ,  Qiyang He

发明人： Yiying Zhang ,  Qiyang He

IPC分类号： H01L21/336 ,  H01L21/469 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

摘要： A method of fabricating a semiconductor device is provided. The method includes forming a gate having a first material on a substrate and a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. A characteristic of a portion of the substrate between adjacent sidewall spacers is changed using the layer of second material and the sidewall spacers as a mask. An isotropic wet etch process is performed to remove the substrate portion with a changed characteristic to form a recess in the substrate. An orientation selective wet etching process is performed on the recess to shape the inner walls of the recess into sigma-shape. Changing a substrate characteristic in conjunction with isotropic wet etching prevents the substrate from being damaged, and therefore can obtain defect free epitaxial SiGe growth performance.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成具有第一材料的栅极和覆盖栅极的第二材料层。 侧壁间隔件形成在门的相对侧上。 使用第二材料层和侧壁间隔物作为掩模来改变相邻侧壁间隔物之间​​的衬底的一部分的特性。 执行各向同性湿法蚀刻工艺以以改变的特性去除衬底部分，以在衬底中形成凹陷。 在凹部上执行取向选择性湿蚀刻工艺，以将凹陷的内壁形成为西格玛形状。 结合各向同性湿蚀刻改变衬底特性防止衬底受损，因此可获得无缺陷的外延SiGe生长性能。

公开(公告)号：US08450166B2

公开(公告)日：2013-05-28

申请号：US13293030

申请日：2011-11-09

申请人： Yiying Zhang ,  Qiyang He

发明人： Yiying Zhang ,  Qiyang He

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3086 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

摘要： Method of fabricating a semiconductor device includes forming a gate having a first material on a substrate and forming a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. The substrate is dry etched using the layer of second material and the sidewall spacers as a mask forming a recess in the substrate between two adjacent gates. A liner oxide layer is formed on inner walls of the recess. The liner oxide layer is removed by isotropic wet etching. Orientation selective wet etching is performed on the recess to shape the inner wall of the recess so as to cause the inner wall of the recess to be sigma-shaped. By removing the substrate portions having lattice defects due to dry etching through oxidation and wet etching, defect-free epitaxial growth performance is realized.

摘要翻译： 制造半导体器件的方法包括在衬底上形成具有第一材料的栅极并形成覆盖栅极的第二材料层。 侧壁间隔件形成在门的相对侧上。 使用第二材料层和侧壁间隔物作为在两个相邻栅极之间的衬底中形成凹陷的掩模进行干蚀刻。 衬垫氧化物层形成在凹槽的内壁上。 通过各向同性湿蚀刻除去衬里氧化物层。 在凹部上进行取向选择性湿蚀刻，以形成凹部的内壁，从而使凹部的内壁成为西格玛形状。 通过通过氧化和湿蚀刻去除由于干蚀刻而具有晶格缺陷的衬底部分，实现了无缺陷的外延生长性能。

公开(公告)号：US08741744B2

公开(公告)日：2014-06-03

申请号：US13240637

申请日：2011-09-22

申请人： Qiyang He ,  Yiying Zhang

发明人： Qiyang He ,  Yiying Zhang

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/32139 ,  G03F7/0035 ,  H01L21/28123 ,  H01L27/0203

摘要： This disclosure is directed to a method of forming a gate pattern and a semiconductor device. The method comprises: providing a plurality of stacked structures which are parallel to each other and extend continuously in a first direction, and which are composed of a gate material bar and an etching barrier bar thereon; leaving second resist regions between gaps to be formed adjacent to each other across gate bars by a second photolithography process; selectively removing the etching barrier bars by a second etching process; forming a third resist layer having a plurality of openings parallel to each other and extending continuously in a second direction substantially perpendicular to the first direction by a third photolithography process; and forming the gate pattern by a third etching process. The method is capable of having a larger photolithography process window and better controlling the shape and size of a gate pattern.

摘要翻译： 本公开涉及形成栅极图案和半导体器件的方法。 该方法包括：提供彼此平行并在第一方向上连续延伸的多个堆叠结构，并且由其上的栅极材料棒和蚀刻阻挡条构成; 在通过第二光刻工艺在栅棒之间彼此相邻形成的间隙之间留下第二抗蚀剂区域; 通过第二蚀刻工艺选择性地去除蚀刻阻挡条; 形成具有彼此平行的多个开口的第三抗蚀剂层，并通过第三光刻工艺在基本上垂直于第一方向的第二方向上连续延伸; 以及通过第三蚀刻工艺形成栅极图案。 该方法能够具有更大的光刻工艺窗口并且更好地控制栅极图案的形状和尺寸。