Amplifier with switchable transformer

    公开(公告)号:US12132455B2

    公开(公告)日:2024-10-29

    申请号:US17647534

    申请日:2022-01-10

    CPC classification number: H03F3/245 H03F2200/451 H03F2200/537

    Abstract: In certain aspects, an apparatus includes a first amplifier having a first output and a second output, and a transformer. The transformer includes a first switchable inductor coupled between the first output and the second output, a first capacitor coupled in parallel with the first switchable inductor, a second switchable inductor magnetically coupled to the first switchable inductor, a second capacitor coupled in parallel with the second switchable inductor, a third switchable inductor magnetically coupled to the first switchable inductor, and a third capacitor coupled in parallel with the third switchable inductor.

    Doherty transceiver interface
    3.
    发明授权

    公开(公告)号:US12301170B2

    公开(公告)日:2025-05-13

    申请号:US17481559

    申请日:2021-09-22

    Abstract: A transceiver interface for a phased array element includes a first magnetic circuit having a primary coil and a secondary coil, a second magnetic circuit having a primary coil, a secondary coil and a tertiary coil, a main amplifier path and an auxiliary amplifier path, the main amplifier path coupled to the primary coil of the second magnetic circuit and configured to receive a quadrature signal, the main amplifier path configured to provide a quadrature output signal, the auxiliary amplifier path coupled to the primary coil of the first magnetic circuit and configured to receive an in-phase signal, the auxiliary amplifier path configured to provide an in-phase output signal, a selectable output circuit configured to selectively combine the in-phase output signal and the quadrature output signal, and a low noise amplifier (LNA) coupled to the tertiary coil of the second magnetic circuit.

    Reducing Parasitic Capacitance
    4.
    发明公开

    公开(公告)号:US20240097619A1

    公开(公告)日:2024-03-21

    申请号:US17932403

    申请日:2022-09-15

    CPC classification number: H03F1/26 H03F3/45475 H03F2200/372

    Abstract: An apparatus is disclosed for reducing parasitic capacitance. In an example aspect, an apparatus includes an amplifier having a differential cascode configuration. Each stack of the amplifier includes a first transistor configured to operate as an input stage and a second transistor configured to operate as a cascode stage. The first and second transistors each include two channel terminal regions having a doping type that is uniform across the two channel terminal regions. Surfaces of first channel terminal regions of the first and second transistors abut a first and second quantity of electrical contacts, respectively. Second channel terminal regions of the first and second transistors form a floating region at a floating node. Each of the first quantity of electrical contacts and the second quantity of electrical contacts is greater than a third quantity of electrical contacts abutting a surface of the floating region.

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