Doherty transceiver interface
    1.
    发明授权

    公开(公告)号:US12301170B2

    公开(公告)日:2025-05-13

    申请号:US17481559

    申请日:2021-09-22

    Abstract: A transceiver interface for a phased array element includes a first magnetic circuit having a primary coil and a secondary coil, a second magnetic circuit having a primary coil, a secondary coil and a tertiary coil, a main amplifier path and an auxiliary amplifier path, the main amplifier path coupled to the primary coil of the second magnetic circuit and configured to receive a quadrature signal, the main amplifier path configured to provide a quadrature output signal, the auxiliary amplifier path coupled to the primary coil of the first magnetic circuit and configured to receive an in-phase signal, the auxiliary amplifier path configured to provide an in-phase output signal, a selectable output circuit configured to selectively combine the in-phase output signal and the quadrature output signal, and a low noise amplifier (LNA) coupled to the tertiary coil of the second magnetic circuit.

    DUAL STAGE LOW NOISE AMPLIFIER FOR MULTIBAND RECEIVER
    4.
    发明申请
    DUAL STAGE LOW NOISE AMPLIFIER FOR MULTIBAND RECEIVER 有权
    双级接收机的双级低噪声放大器

    公开(公告)号:US20160087587A1

    公开(公告)日:2016-03-24

    申请号:US14491833

    申请日:2014-09-19

    Abstract: A dual stage LNA for use in multiband receivers is disclosed. In an exemplary embodiment, an apparatus includes a plurality of first stage amplifiers having a plurality of first stage output ports, respectively, to output first stage amplified voltage mode signals. The apparatus also includes a plurality of second stage amplifiers having a plurality of second stage input ports, respectively, and second stage output ports to output amplified current mode signals. The apparatus also includes a switch apparatus having input terminals connected to the first stage output ports and output terminals connected to the second stage input ports, the switch apparatus to connect selected second stage input ports to selected first stage output ports.

    Abstract translation: 公开了一种用于多频带接收机的双级LNA。 在示例性实施例中,装置包括分别具有多个第一级输出端口的多个第一级放大器,用于输出第一级放大的电压模式信号。 该装置还包括分别具有多个第二级输入端口的多个第二级放大器和用于输出放大的电流模式信号的第二级输出端口。 该装置还包括具有连接到第一级输出端口的输入端子和连接到第二级输入端口的输出端子的开关装置,该开关装置将所选择的第二级输入端口连接到所选择的第一级输出端口。

    Oscillator feedthrough calibration

    公开(公告)号:US12255586B2

    公开(公告)日:2025-03-18

    申请号:US18060295

    申请日:2022-11-30

    Abstract: An apparatus is disclosed for oscillator feedthrough calibration, such as a component arrangement that can be calibrated to account for signal leakage from an oscillator coupled to a mixer circuit. In example aspects, the apparatus includes a mixer circuit having a first stage, a second stage, and tuning circuitry. The first stage includes at least one transistor coupled between a mixer input and a mixer output. The second stage includes one or more transistors coupled between the at least one transistor of the first stage and the mixer output. The one or more transistors are also coupled between a local oscillator signal input and the mixer output. The tuning circuitry includes at least one current source coupled to the at least one transistor of the first stage.

    Split chaining for large phase array systems

    公开(公告)号:US11942971B2

    公开(公告)日:2024-03-26

    申请号:US17686794

    申请日:2022-03-04

    CPC classification number: H04B1/0057 H04B1/0035 H04B1/0483 H04B2001/0408

    Abstract: Aspects described herein include devices and methods with chain routing of signals for massive antenna arrays. In some aspects, an apparatus is provided that includes a first millimeter wave (mmW) transceiver having a first port, a second port, one or more antenna elements, a plurality of chain mmW transceiver ports, and switching circuitry. The switching circuitry is controllable by control data to route portions of a merged clock and data signal and a merged control and data signal between a first route between the one or more antenna elements and the first port and a second route between the one or more antenna elements and the second port and a third route between the first port and the plurality of chain mmW transceiver ports and a fourth route between the second port and the plurality of chain mmW transceiver ports.

Patent Agency Ranking