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公开(公告)号:US11923323B2
公开(公告)日:2024-03-05
申请号:US17843986
申请日:2022-06-18
Applicant: QUALCOMM Incorporated
Inventor: Ibrahim Ramez Chamas , Mohamed Abouzied , Bhushan Shanti Asuri
CPC classification number: H01L23/66 , H01L23/562 , H01L23/585 , H01L24/13 , H03H7/42 , H01L2223/6655 , H01L2223/6677 , H01L2224/13026 , H01L2224/13147 , H01L2924/19051 , H01L2924/3512 , H04B1/40
Abstract: An RF flip chip is provided in which a local bump region adjacent a die corner includes a balun having a centrally-located bump.
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公开(公告)号:US11917601B2
公开(公告)日:2024-02-27
申请号:US17450420
申请日:2021-10-08
Applicant: QUALCOMM Incorporated
Inventor: Mihir Vijay Laghate , Revathi Sundara Raghavan , Bhushan Shanti Asuri
IPC: H04W72/044 , H04W24/10 , H04B7/08
CPC classification number: H04W72/046 , H04B7/08 , H04W24/10
Abstract: A method of wireless communication includes receiving a first beam using a first antenna device during an occasion of a reference signal. The method further includes receiving a second beam using a second antenna device that is distinct from the first antenna device during the occasion of the reference signal. Receiving the first beam and the second beam includes inputting, to a modem, a representation of a combination of the first beam and the second beam. Receiving the first beam and the second beam further includes generating, by the modem based on the representation, a first signal associated with the first beam using a first parameter associated with the first antenna device and a second signal associated with the second beam using a second parameter associated with the second antenna device.
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公开(公告)号:US11646277B2
公开(公告)日:2023-05-09
申请号:US17118253
申请日:2020-12-10
Applicant: QUALCOMM Incorporated
Inventor: Muhammad Hassan , Bhushan Shanti Asuri , Jeremy Darren Dunworth , Ravi Sridhara
CPC classification number: H01L23/60 , H03F3/195 , H03F3/245 , H03F2200/318 , H03F2200/441 , H03F2200/451 , H03F2200/541
Abstract: According to certain aspects, a chip includes a pad, a power amplifier, a transformer coupled between an output of the power amplifier and the pad, a transistor coupled between the transformer and a ground, and a first clamp circuit coupled between a gate of the transistor and a drain of the transistor.
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公开(公告)号:US11380988B2
公开(公告)日:2022-07-05
申请号:US17098319
申请日:2020-11-13
Applicant: QUALCOMM Incorporated
Inventor: Muhammad Hassan , Jeremy Goldblatt , Bhushan Shanti Asuri , Jeremy Darren Dunworth , Abdellatif Bellaouar , Ravi Sridhara , Jorge Garcia
Abstract: In some aspects, an apparatus includes a transformer including a first inductor, a second inductor, and a third inductor. The apparatus also includes a power amplifier coupled to the first inductor, a first antenna coupled to a first terminal of the second inductor, a second antenna coupled to a second terminal of the second inductor, a first switch coupled between the first terminal of the second inductor and a ground, a second switch coupled between the second terminal of the second inductor and the ground, and a low-noise amplifier coupled to the third inductor.
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公开(公告)号:US11349503B2
公开(公告)日:2022-05-31
申请号:US17001568
申请日:2020-08-24
Applicant: Qualcomm Incorporated
Inventor: Laya Mohammadi , Chirag Dipak Patel , Bhushan Shanti Asuri
Abstract: An apparatus is disclosed for phase-shifting signals with a compensation circuit. In example implementations, an apparatus for phase-shifting signals includes a phase shifter having a first port and a second port. The phase shifter also includes a signal phase generator, a compensation circuit, and a vector modulator. The compensation circuit includes a first capacitor with a first capacitance and a second capacitor with a second capacitance. The first capacitance is different from the second capacitance. The signal phase generator is coupled between the first port and the compensation circuit. The vector modulator is coupled between the compensation circuit and the second port.
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公开(公告)号:US20210091819A1
公开(公告)日:2021-03-25
申请号:US16578096
申请日:2019-09-20
Applicant: QUALCOMM Incorporated
Inventor: Bhushan Shanti Asuri , Yiwu Tang , Shrenik Patel
Abstract: Wireless communication system may be configured to use different frequency bands for uplink communication and downlink communication. For example, a wireless system may use multiple frequency bands for downlink with carrier aggregation, and the wireless system may use only one frequency band for uplink. Up-conversion and down-conversion between baseband signals and RF signals, using a fixed frequency local oscillator signal may cause energy leak to an adjacent frequency band during transmission of signal and may result in interferences to other radio communication devices using the adjacent bands. To limit the amount of energy that leaks out of its assigned radio frequency bands, the UE may use local oscillator signals with different frequencies for up-conversion and down-conversion and may switch the frequencies of the local oscillator signals between reception of downlink signals and transmission of uplink signals.
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公开(公告)号:US10305522B1
公开(公告)日:2019-05-28
申请号:US15962844
申请日:2018-04-25
Applicant: QUALCOMM Incorporated
Inventor: Bhushan Shanti Asuri , Krishnaswamy Thiagarajan
Abstract: A communication circuit may include mixers configured to generate voltage mode outputs. The communication circuit may further include voltage nodes configured to sum the voltage mode outputs produced by the mixers to generate intermediate voltage mode signals. The communication circuit may further include transconductors configured to convert the intermediate voltage mode signals to intermediate current mode signals. The communication circuit may further include at least one current node configured to sum the intermediate current mode signals to generate at least one mixer output signal.
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公开(公告)号:US20190089358A1
公开(公告)日:2019-03-21
申请号:US15711708
申请日:2017-09-21
Applicant: Qualcomm Incorporated
CPC classification number: H03L7/07 , H03K5/133 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/093 , H03L7/0995
Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.
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公开(公告)号:US12261577B2
公开(公告)日:2025-03-25
申请号:US17356424
申请日:2021-06-23
Applicant: QUALCOMM Incorporated
Inventor: Jeremy Goldblatt , Arul Balasubramaniyan , Chinmaya Mishra , Damin Cao , Bhushan Shanti Asuri
Abstract: A peak detector for a power amplifier is provided that includes a threshold voltage detector configured to pulse a detection current in response to an amplified output signal from the amplifier exceeding a peak threshold. A plurality of such peak detectors may be integrated with a corresponding plurality of power amplifiers in a transmitter. Should any peak detector assert an alarm signal or more than a threshold number of alarm signals during a given period, a controller reduces a gain for the plurality of power amplifiers.
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公开(公告)号:US11656254B2
公开(公告)日:2023-05-23
申请号:US16932589
申请日:2020-07-17
Applicant: QUALCOMM Incorporated
Inventor: Abdellatif Bellaouar , Arul Balasubramaniyan , Gurkanwal Singh Sahota , Muhammad Hassan , Jorge Garcia , Bhushan Shanti Asuri , Ravi Sridhara , Omar Essam El-Aassar , Chinmaya Mishra
IPC: G01R21/10 , G01R21/133 , H03F3/45 , H03M1/12
CPC classification number: G01R21/10 , G01R21/133 , H03F3/45475 , H03F2200/171 , H03F2200/294 , H03F2200/451 , H03M1/12
Abstract: In certain aspects, a method is provided for measuring power using a resistive element coupled between a power amplifier and an antenna. The method includes squaring a voltage from a first terminal of the resistive element to obtain a first signal, squaring a voltage from a second terminal of the resistive element to obtain a second signal, and generating a measurement signal based on a difference between the first signal and the second signal. In some implementations, the resistive element is implemented with a power switch.
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