公开(公告)号：US20200168604A1

公开(公告)日：2020-05-28

申请号：US16777639

申请日：2020-01-30

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Michael Joseph BRUNOLLI ,  Christine Sung-An HAU-RIEGE ,  Mickael MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/482 ,  H01L23/528

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

公开(公告)号：US20150054568A1

公开(公告)日：2015-02-26

申请号：US13975185

申请日：2013-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi RASOULI ,  Michael Joseph BRUNOLLI ,  Christine Sung-An HAU-RIEGE ,  Mickael MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Abstract translation: 具有多个PMOS晶体管的CMOS器件，每个具有PMOS漏极和多个NMOS晶体管，每个具有NMOS漏极包括在长度方向上延伸的互连级上的第一互连，以将PMOS漏极连接在一起。 互连级上的第二互连在长度方向上延伸以将NMOS漏极连接在一起。 在至少一个附加互连级上的一组互连将第一互连和第二互连耦合在一起。 互连层上的第三互连件垂直于长度方向延伸，并且从互连组中偏移以将第一互连和第二互连连接在一起。