公开(公告)号：US20180183439A1

公开(公告)日：2018-06-28

申请号：US15393180

申请日：2016-12-28

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana SAHU ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM ,  Mickael MALABRY ,  Mukul GUPTA

IPC: H03K19/0948 ,  H01L27/118 ,  H01L23/528 ,  H01L23/522

CPC classification number: H03K19/0948 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11807 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2027/11888

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US20200266821A1

公开(公告)日：2020-08-20

申请号：US15929520

申请日：2020-05-07

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana SAHU ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM ,  Mickael MALABRY ,  Mukul GUPTA

IPC: H03K19/0948 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US20190173473A1

公开(公告)日：2019-06-06

申请号：US16267289

申请日：2019-02-04

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana SAHU ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM ,  Mickael MALABRY ,  Mukul GUPTA

IPC: H03K19/0948 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L27/118

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US20180074117A1

公开(公告)日：2018-03-15

申请号：US15265744

申请日：2016-09-14

Applicant: QUALCOMM Incorporated

Inventor： Rami SALEM ,  Lesly Zaren V. ENDRINAL ,  Hyeokjin LIM ,  Hadi BUNNALIM ,  Robert KIM ,  Lavakumar RANGANATHAN ,  Mickael MALABRY

IPC: G01R31/28 ,  H01L23/50 ,  H01L27/02 ,  H01L27/088 ,  G01R31/311

CPC classification number: G01R31/2891 ,  G01R31/2834 ,  G01R31/311 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2223/54426

Abstract: A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.

公开(公告)号：US20160370699A1

公开(公告)日：2016-12-22

申请号：US15182510

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Hyeokjin Bruce LIM ,  Ohsang KWON ,  Mickael MALABRY ,  Jingwei ZHANG ,  Raymond George STEPHANY ,  Haining YANG ,  Kern RIM ,  Stanley Seungchul SONG ,  Mukul GUPTA ,  Foua VANG

IPC: G03F1/70 ,  G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5068

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

Abstract translation: 在本公开的一个方面，提供了一种方法，计算机可读介质和用于分配多个图案化处理的特征颜色的装置。 该装置接收集成电路布局信息，该信息包括一组特征的集合，以及针对特征集合的第一特征集的每个特征的多种颜色的分配颜色。 另外，该装置对特征的第二子集执行颜色分解，以将颜色分配给第二特征子集中的特征。 特征的第二子集包括不包括在具有分配颜色的特征的第一子集中的特征集合中的特征。

公开(公告)号：US20200168604A1

公开(公告)日：2020-05-28

申请号：US16777639

申请日：2020-01-30

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Michael Joseph BRUNOLLI ,  Christine Sung-An HAU-RIEGE ,  Mickael MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/482 ,  H01L23/528

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

公开(公告)号：US20150054568A1

公开(公告)日：2015-02-26

申请号：US13975185

申请日：2013-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi RASOULI ,  Michael Joseph BRUNOLLI ,  Christine Sung-An HAU-RIEGE ,  Mickael MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Abstract translation: 具有多个PMOS晶体管的CMOS器件，每个具有PMOS漏极和多个NMOS晶体管，每个具有NMOS漏极包括在长度方向上延伸的互连级上的第一互连，以将PMOS漏极连接在一起。 互连级上的第二互连在长度方向上延伸以将NMOS漏极连接在一起。 在至少一个附加互连级上的一组互连将第一互连和第二互连耦合在一起。 互连层上的第三互连件垂直于长度方向延伸，并且从互连组中偏移以将第一互连和第二互连连接在一起。