公开(公告)号：US20180211957A1

公开(公告)日：2018-07-26

申请号：US15927539

申请日：2018-03-21

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Michael BRUNOLLI ,  Christine HAU-RIEGE ,  Mickael Sebtastien Alain MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.

公开(公告)号：US20150235948A1

公开(公告)日：2015-08-20

申请号：US14274184

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Zhongze WANG ,  Ohsang KWON ,  Kern RIM ,  John Jianhong ZHU ,  Xiangdong CHEN ,  Foua VANG ,  Raymond George STEPHANY ,  Choh Fei YEAP

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42312 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Abstract translation: 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。

公开(公告)号：US20180342515A1

公开(公告)日：2018-11-29

申请号：US16057036

申请日：2018-08-07

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US20160370699A1

公开(公告)日：2016-12-22

申请号：US15182510

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Hyeokjin Bruce LIM ,  Ohsang KWON ,  Mickael MALABRY ,  Jingwei ZHANG ,  Raymond George STEPHANY ,  Haining YANG ,  Kern RIM ,  Stanley Seungchul SONG ,  Mukul GUPTA ,  Foua VANG

IPC: G03F1/70 ,  G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5068

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

Abstract translation: 在本公开的一个方面，提供了一种方法，计算机可读介质和用于分配多个图案化处理的特征颜色的装置。 该装置接收集成电路布局信息，该信息包括一组特征的集合，以及针对特征集合的第一特征集的每个特征的多种颜色的分配颜色。 另外，该装置对特征的第二子集执行颜色分解，以将颜色分配给第二特征子集中的特征。 特征的第二子集包括不包括在具有分配颜色的特征的第一子集中的特征集合中的特征。

公开(公告)号：US20150333008A1

公开(公告)日：2015-11-19

申请号：US14279250

申请日：2014-05-15

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Foua VANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L23/535 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

Abstract translation: 标准单元CMOS器件包括具有由栅极互连形成的栅极的金属氧化物半导体晶体管。 栅极互连沿第一方向延伸。 该器件还包括向晶体管提供功率的电源轨。 电源轨在与第一方向正交的第二方向上延伸。 该装置还包括在电源轨之间延伸的M1层互连。 M1层互连中的至少一个耦合到至少一个晶体管。 M1层互连平行于栅极互连并仅在第一方向上延伸。

公开(公告)号：US20150301973A1

公开(公告)日：2015-10-22

申请号：US14484137

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Kern RIM ,  Stanley Seungchul SONG ,  Xiangdong CHEN ,  Raymond George Stephany ,  John Jianhong ZHU ,  Ohsang KWON ,  Esin TERZIOGLU ,  Choh Fei YEAP

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

Abstract translation: 设计导电互连的方法包括至少部分地基于互连迹线间距和指定单元高度的整数倍来确定残余间隔值。 该方法还包括将剩余间隔分配到互连迹线间距内的至少一个互连迹线宽度或互连迹线空间。

公开(公告)号：US20180122824A1

公开(公告)日：2018-05-03

申请号：US15855996

申请日：2017-12-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Foua VANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

公开(公告)号：US20170221826A1

公开(公告)日：2017-08-03

申请号：US15493008

申请日：2017-04-20

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

公开(公告)号：US20160351490A1

公开(公告)日：2016-12-01

申请号：US14723357

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON

IPC: H01L23/528 ,  H01L27/088

CPC classification number: H01L23/528 ,  G06F1/10 ,  G06F17/5068 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11879

Abstract: A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.

Abstract translation: MOS器件包括第一，第二，第三和第四互连。 第一互连在第一方向上在第一轨道上延伸。 第一互连配置在金属层中。 第二互连在第一方向上在第一轨道上延伸。 第二互连配置在金属层中。 第三互连在第一方向上的第二轨道上延伸。 第三互连配置在金属层中。 第二条轨道平行于第一条轨道。 第三互连耦合到第二互连。 第二和第三互连被配置为提供第一信号。 第四互连在第一方向上在第二轨道上延伸。 第四互连配置在金属层中。 第四互连耦合到第一互连。 第一和第四互连配置成提供与第一信号不同的第二信号。

公开(公告)号：US20150287709A1

公开(公告)日：2015-10-08

申请号：US14247214

申请日：2014-04-07

Applicant: QUALCOMM Incorporated

Inventor： HariKrishna CHINTARLAPALLI REDDY ,  Son LE ,  Ohsang KWON ,  Vijayalakshmi RANGANNA

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L27/092

Abstract: A double patterned CMOS device includes a first set of stacked transistors, a second set of stacked transistors, and a set of transistors. The first set of stacked transistors includes first and second transistors. The first transistor has a first transistor active region and the second transistor has a second transistor active region. The second set of stacked transistors is adjacent the first set of stacked transistors. The second set of stacked transistors includes third and fourth transistors. The third transistor has a third transistor active region and the fourth transistor has a fourth transistor active region. The set of transistors is adjacent the first set of stacked transistors. The set of transistors includes a fifth transistor. The fifth transistor has a fifth transistor active region. The first, second, third, and fourth transistor active regions satisfy certain distance relationships from each other.

Abstract translation: 双重图案化CMOS器件包括第一组堆叠晶体管，第二组堆叠晶体管和一组晶体管。 第一组堆叠晶体管包括第一和第二晶体管。 第一晶体管具有第一晶体管有源区，而第二晶体管具有第二晶体管有源区。 第二组堆叠晶体管与第一组堆叠晶体管相邻。 第二组堆叠晶体管包括第三和第四晶体管。 第三晶体管具有第三晶体管有源区，第四晶体管具有第四晶体管有源区。 该组晶体管与第一组堆叠晶体管相邻。 晶体管组包括第五晶体管。 第五晶体管具有第五晶体管有源区。 第一，第二，第三和第四晶体管有源区域彼此满足一定的距离关系。