公开(公告)号：US20160065232A1

公开(公告)日：2016-03-03

申请号：US14475852

申请日：2014-09-03

Applicant: QUALCOMM INCORPORATED

Inventor： Elias Hani Dagher ,  Kentaro Yamamoto ,  Dinesh Jagannath Alladi

IPC: H03M1/34

CPC classification number: H03M1/34 ,  H03M3/30 ,  H03M3/37 ,  H03M3/426 ,  H03M3/454 ,  H03M3/458 ,  H03M3/464

Abstract: In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

Abstract translation: 在一个实施例中，电路包括被配置为将模拟输入信号转换成数字信号的量化器。 量化器包括第一反馈路径，其包括从量化器的输出耦合到耦合到量化器的输入的求和结点的第一数模转换器（DAC）。 第一反馈路径将数字信号转换为第一对应的模拟值，以与求和点处的模拟输入信号组合。 此外，量化器还包括耦合到求和点的多个过剩环路延迟（ELD）补偿路径，其被配置为补偿从量化器的输出耦合到从量化器经由环路滤波器输入的第二反馈路径的过多的环路延迟。 第二反馈路径中的第二DAC将数字信号转换为第二对应的模拟值，以与模拟输入信号组合。

公开(公告)号：US20150244385A1

公开(公告)日：2015-08-27

申请号：US14549445

申请日：2014-11-20

Applicant: QUALCOMM Incorporated

Inventor： Dinesh Jagannath Alladi ,  Omar Hafiz ,  Elias Hani Dagher

IPC: H03M1/06 ,  H03M1/18 ,  H03M1/12

CPC classification number: H03M1/0629 ,  H03M1/1245 ,  H03M1/186 ,  H03M3/344

Abstract: In embodiments, a circuit includes a single-ended input coupled to a first input of a differential filter. The differential filter is coupled to an analog to digital converter (ADC), and the single-ended input includes an input DC bias voltage level and an input signal. A reference generator circuit is coupled to a second input of the differential filter. The reference generator circuit generates a reference bias voltage. The differential filter includes a first filter coupled to the singled ended input and to the ADC and a second filter coupled to the reference generator circuit and to the ADC. The first filter is configured to receive the input DC bias voltage level and input signal. The second filter is configured to receive the reference bias voltage.

Abstract translation: 在实施例中，电路包括耦合到差分滤波器的第一输入的单端输入。 差分滤波器耦合到模数转换器（ADC），单端输入包括输入直流偏置电压电平和输入信号。 参考发生器电路耦合到差分滤波器的第二输入端。 参考发生器电路产生参考偏置电压。 差分滤波器包括耦合到单端输入和ADC的第一滤波器以及耦合到参考发生器电路和ADC的第二滤波器。 第一个滤波器配置为接收输入的直流偏置电压电平和输入信号。 第二滤波器被配置为接收参考偏置电压。

公开(公告)号：US09628103B2

公开(公告)日：2017-04-18

申请号：US14639534

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Yan Wang ,  Dinesh Jagannath Alladi ,  Chieh-Yu Hsieh ,  Elias Hani Dagher

IPC: H03M3/00

CPC classification number: H03M3/32 ,  H03M3/354 ,  H03M3/392 ,  H03M3/45 ,  H03M3/454 ,  H03M3/496

Abstract: A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

公开(公告)号：US09325341B2

公开(公告)日：2016-04-26

申请号：US14475852

申请日：2014-09-03

Applicant: QUALCOMM Incorporated

Inventor： Elias Hani Dagher ,  Kentaro Yamamoto ,  Dinesh Jagannath Alladi

IPC: H03M3/00 ,  H03M1/34

CPC classification number: H03M1/34 ,  H03M3/30 ,  H03M3/37 ,  H03M3/426 ,  H03M3/454 ,  H03M3/458 ,  H03M3/464

Abstract: In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

Abstract translation: 在一个实施例中，电路包括被配置为将模拟输入信号转换成数字信号的量化器。 量化器包括第一反馈路径，其包括从量化器的输出耦合到耦合到量化器的输入的求和结点的第一数模转换器（DAC）。 第一反馈路径将数字信号转换为第一对应的模拟值，以与求和点处的模拟输入信号组合。 此外，量化器还包括耦合到求和点的多个过剩环路延迟（ELD）补偿路径，其被配置为补偿从量化器的输出耦合到从量化器经由环路滤波器输入的第二反馈路径的过多的环路延迟。 第二反馈路径中的第二DAC将数字信号转换为第二对应的模拟值，以与模拟输入信号组合。